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Proposes a call admission control scheme for low earth orbit satellite networks. Purpose of the scheme; Call traffic recasting; Traffic projections.

Presents a study that described a buffer replacement scheme, called Detection-based Adaptive Replacement (DEAR), for effective caching of disk blocks in a computer operating system. Features of the DEAR scheme; Implementation of the DEAR scheme in the FreeBSD operating system; Evaluation of the performance of the DEAR scheme.

We propose a code scratchpad memory (SPM) management technique with demand paging for embedded systems that have no memory management unit. Based on profiling information, a postpass optimizer analyzes and optimizes application binaries in a fully automated process. It classifies the code of the application including libraries into three classes based on a mixed integer linear programming formulation: External code is executed directly from the external memory. Pinned code is loaded into the SPM when the application starts and stays in the SPM. Paged code is loaded into/unloaded from the SPM on demand. We evaluate the proposed technique by running 14 embedded applications both on a cycle-accurate ARM processor simulator and an ARM1136JF-S core. On the simulator, the reference case, a four-way set-associative cache, is compared to a direct-mapped cache and an SPM of comparable die area. On average, we observe an improvement of 12 percent in runtime performance and a 21 percent reduction in energy consumption. On the ARM11 board, the reference case run on the 16-KB four-way set-associative cache is compared to the demand paging solution on the 16-KB SPM, optionally supported by the cache. The measured results show both a runtime performance improvement and a reduction of the energy consumption by 23 percent, on average. [ABSTRACT FROM AUTHOR]

Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered. [ABSTRACT FROM AUTHOR]

Proposes a flash translation layer (FTL) design aimed at mass storage CompactFlash systems. Characteristics of flash memory that make difficult straightforward replacement of magnetic disks; Background flash memory; Description of the log block scheme proposed; Evaluation of the proposed FTL design.

Shows that there exists a spectrum of block replacement policies in computer memory that subsumes the two seemingly unrelated and independent Least Recently Used (LRU) and Least Frequently Used (LFU) policies. Spectrum of implementations of the LRFU that again subsumes the LRU and LFU implementations; Comparison of the LRFU policy with other policies; Combined effects of λ and correlated period on the performance of the LRFU policy.

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach. [ABSTRACT FROM AUTHOR]

Proposes a technique used in the analysis of cache-related preemption delays in fixed-priority preemptive scheduling. Steps which the techniques consists of; Information on real-time systems; Schedulability analysis in fixed-priority scheduling; Details on caches in real-time systems.

Proposes a framework for solving the link assignment problem associated with the use of intersatellite links in low earth orbit satellite networks. Information on the framework; What is allowed by the finite state automation based framework; Details on what is used by Iridium and Calling low earth orbit satellites.