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A system-level design methodology is proposed to reduce the sensitivity of an integrated zero-IF receiver, including the analog-to-digital converter, to performance variations of its components due to process spreading. Describing each stage of the receiver by three parameters of voltage gain, noise, and nonlinearity, whose variations represent all lower-level sources of variability, the sensitivity of the overall performance to the variations of these parameters is calculated. Three design approaches are proposed, analyzed, and compared for reducing these sensitivities. Statistical and corner simulations are performed to confirm the validity of the proposed guidelines showing significant improvement in the yield of the designs. [ABSTRACT FROM PUBLISHER]

The future of all kinds of applications that require a submilliwatt consumption strictly depends on the capability to meet design specifications at the minimum power costs. While several computer-aided-design tools are present to estimate the power consumption of modern ICs at transistor level, it is very difficult to predict the power at higher level. Given the reduced time-to-market of modern communication devices, it is very often needed to have accurate power estimations prior to the transistor-level design. Allocating a too conservative power budget to a block implies a possible poor tradeoff between the specifications of building blocks that constitute the system and their power consumption. For future power-constrained wireless devices (like wireless nodes in sensor networks), it is very important to have high-level models which can help the designer with the initial high-level choices without going into transistor-level design. One of the important blocks in modern communication devices, particularly for spread-spectrum systems, is the frequency synthesizer. In this paper, the first power-consumption model for an ultralow-power ROM-based direct digital frequency synthesizer has been developed, which can help the designer in the power optimization at a high level prior to transistor implementation. [ABSTRACT FROM AUTHOR]

Under antenna mismatch conditions at high output power, voltage clipping (due to collector voltage saturation) is the main cause of power amplifier linearity degradation. To preserve linearity under mismatch three adaptive methods are presented that make use of the detected minimum collector peak voltage. This detected signal controls either the amplifier output power, load-line, or supply voltage. These concepts are generalized analytically, and calculated results compare well to simulations. Measurements demonstrate am error vector magnitude reduction of 5% and an adjacent channel power ratio improvement of 10 dB at a voltage standing wave ratio of 4 for an EDGE amplifier with adaptively controlled output power. These adaptive methods offer a cost and size effective alternative to the use of an isolator. [ABSTRACT FROM AUTHOR]

An energy-efficient fast start-up method for crystal oscillators is presented, which enables aggressive duty-cycled operation of IoT radios to minimize overall power consumption. A digitally controlled crystal oscillator using the proposed start-up technique in 90-nm CMOS is presented. Thanks to the dynamically adjusted load, the negative resistance is boosted, achieving a $13\times $ start-up time reduction and an overall power of $95\mu \text{W}$ for a 24-MHz crystal oscillator at 1 V. A fully autonomous feedback loop detects the oscillators envelop and adjusts the load capacitance at start-up. Thanks to the low-power start-up circuits, both the start-up time and the start-up energy are reduced. In addition, the robustness and versatility of the proposed method is verified by measuring quartz crystals with different frequencies and quality factors, as well as measuring against temperature, supply voltage, and load capacitance variations. [ABSTRACT FROM AUTHOR]

Most wireless battery-operated devices spend more energy receiving than transmitting. Hence, minimizing the power dissipation in the receiver front end, which, in many cases, is the prominent power consuming part of the receiver, is an important challenge. This paper addresses this challenge by solving two closely related optimization problems. Firstly, we optimize the overall power dissipation in an RF front end consisting of a chain of building blocks to satisfy required overall specifications in gain, linearity and noise figure. We extend this into a second optimization problem, namely to maximize the transmission rate that the receiver can accommodate for a given available receiver battery power budget. In fact, the ratio of this transmission rate vs the available receiver power budget serves as the figure-of-merit that allows a formal optimization where, in particular, the (adjacent channel) interference is a critical factor. Our results include closed-form analytical solutions for certain cases. For high signal power, where the noise is limited by interference, the largest bit/s/Hz per nJ drawn from receiver is reached for a transmission rate of 2.3 bits/s/Hz, irrespective of interference power. Numerical results using practical circuit blocks with 90 nm and 65 nm technologies are in close agreement with the analytical results. [ABSTRACT FROM AUTHOR]

In energy-constrained applications like Body Area Networks (BAN) receiver performance is traded for lower power consumption. The limited receiver performance will deteriorate the output signal-to-noise-ratio (SNR) and bit-error-rate (BER) of the receiver. In this paper we present closed-form output SNR and BER models of a non-ideal receiver front-end with limiter-discriminator demodulator for binary FSK. The presented model is very useful in defining the minimally required receiver specifications. Moreover, the models are useful for gaining insight into the influences of the receiver impairments on its performance. In the models, the gain and phase imbalances between the in-phase and quadrature-phase paths as well as the receiver generated noise and the phase noise produced by the local frequency reference are taken into account. This paper shows that the gain and phase imbalances shift the FM threshold to higher carrier-to-noise-ratios (CNR) and only have small influence on the SNR above threshold. On the other hand, receiver generated noise reduces the output SNR both below and above the FM threshold, and phase noise limits the maximum output SNR. Additionally, a trade-off between the FSK frequency deviation and phase noise robustness is derived. [ABSTRACT FROM PUBLISHER]

We present a low-power (382 \mu W) body area network receiver operating in the 900 MHz band. The wideband FSK receiver supports bit rates up to 625 kbps. To save power, the power consuming phase-locked-loop (PLL) is replaced by an energy efficient digital automatic frequency control (AFC) loop. The AFC acts as a low-bandwidth frequency-locked-loop (FLL), using the FSK demodulator as frequency detector; the measured frequency offset is fed back to the on-chip digitally controlled oscillator. To further decrease the power consumption, the LNA is removed, the passive mixer being the first circuit in the receiver front-end. The mixer-first topology increases the linearity compared to injection-locked and envelope detector based receivers. Additionally, analytical passive mixer transducer power gain and noise figure models are presented which are used to obtain an optimal mixer-first design. We achieve a -81~dBm sensitivity at a bit rate of 12.5 kbps. [ABSTRACT FROM PUBLISHER]

The link quality of mobile phones suffers from antenna mismatch due to fluctuating body effects. Techniques for adaptive control of impedance-matching L networks are presented, which provide automatic compensation of antenna mismatch. To secure reliable convergence, a cascade of two control loops is proposed for independent control of the real and imaginary parts of impedance. A secondary feedback path is used to enforce operation into a stable region when needed. These techniques exploit the basic properties of tunable series and parallel LC networks. A generic quadrature detector that offers a power-independent orthogonal reading of the complex impedance value is presented, which is used for direct control of variable capacitors. This approach renders calibration and elaborate software computation superfluous and allows for autonomous operation of adaptive antenna-matching modules. [ABSTRACT FROM AUTHOR]