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The implementation of a "superjunction" collector design in a silicon--germaniumheterojunction bipolar transistor technology is explored for enhancing breakdown performance. The superjunction collector is formed via the placement of a series of alternating the p/xn-doped layers in the collector-base space charge region and is used to reduce avalanche generation leading to breakdown. An overview of the physics underlying superjunction collector operation is presented, together with TCAD simulations, and a parameterization methodology is developed to explore the limits of the superjunction collector performance. Measured data demonstrate the limitations explored in simulation. [ABSTRACT FROM AUTHOR]

A physics-based silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) aging model for mixed-mode stress based on the lucky-electron model and reaction-diffusion theory is developed for integration with compact models. An effective aging parameter extraction method is described, and the aging model parameters are fit for a modern SiGe HBT platform. The aging model is implemented as a wrapper in the Cadence Spectre circuit simulator. Device-level aging simulations are shown to be well-matched to measured degradation data. The aging model is further used to explore the effects of aging on a simple current mirror circuit, showing a decrease in mirror ratio with degradation. [ABSTRACT FROM PUBLISHER]

We investigate and compare the hot-carrier degradation of SiGe HBTs under both traditional mixed-mode electrical stress conditions and high-current electrical stress conditions using measured stress data and an in-depth analysis of the underlying degradation mechanisms. While large electric fields are the driving force in mixed-mode hot-carrier degradation, the Auger recombination process is shown to be the hot-carrier source under high-current stress conditions. Auger hot-carrier degradation shows a positive temperature dependence, unlike mixed-mode degradation, due to the temperature dependence of Auger recombination and its energy distribution function. We also use calibrated TCAD simulations to explain an unexpected stress threshold behavior that occurs due to the formation of a potential well in the neutral base region, and to explore a field-compression effect at the collector/subcollector junction that contributes to trap formation at the shallow trench isolation oxide interface. [ABSTRACT FROM PUBLISHER]

We investigate high current stress mechanisms and demonstrate how Auger hot carriers can damage both oxide interfaces and polysilicon regions of the emitter and base. A new current gain enhancement (CGE) effect is proposed, which involves hot-carrier damage to the polysilicon emitter and extrinsic base leading to the degradation of the associated minority carrier mobilities. We demonstrate the different CGE mechanisms in SiGe HBTs under forward and inverse modes of operation. The hot-carrier damage responsible for CGE at high injection is explored in depth with the help of TCAD simulations. Evidence for this effect has been gathered with good statistical significance from various stress conditions, various technologies, complimentary (NPN + PNP) devices, and from dc and ac measurements. The new polysilicon degradation mechanism proposed in this paper has been generalized and is important for accurately modeling the changes in base resistance and current gain ( $\beta$ ) at high injection, where circuits are typically biased to extract maximum device performance. [ABSTRACT FROM AUTHOR]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

This paper presents the results of an investigation of the steady-state safe operating conditions for large-signal silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) circuits. By calculating capacitive currents within the intrinsic transistor, avalanche inducing currents through the transistor junctions are isolated and then compared with dc instability points established through simulation and measurement. In addition, calibrated technology computer-aided design simulations are used to provide further insight into the differences between RF and dc operation and stress conditions. The ability to swing the terminals of a SiGe HBT beyond the static $I$ – $V$ conditions coincident with catastrophic breakdown is explained. Furthermore, hot-carrier effects are also compared from multiple perspectives, with supporting data taken from fully realized $X$ -band and $C$ -band cascode driver amplifiers. This analysis provides microwave circuit designers with the framework necessary to better understand the full-voltage-swing potential of a given SiGe HBT technology and the resultant hot carrier damage under RF operation. [ABSTRACT FROM AUTHOR]

This paper provides insight into the transport mechanisms of the collector current in SiGe HBTs operating at cryogenic temperatures and compares three technology generations of devices. Based on the experimental data, a method to differentiate direct tunneling from quasi-ballistic transport is proposed. Measurements indicate that direct tunneling becomes more significant at cryogenic temperatures. The effects of technology scaling on the direct tunneling were investigated using TCAD. Direct tunneling was found to be sensitive to the base width and the Ge profile. It is predicted that without an increase in the Ge content, direct tunneling may dominate over quasi-ballistic transport at the limits of technology scaling. [ABSTRACT FROM AUTHOR]

The effects of negative feedback, both external and internal, on single event transients (SETs) in SiGe HBT analog circuits are investigated. In order to examine internal negative feedback effects, basic common-emitter NPN current mirrors, with and without emitter degeneration resistors, are utilized. A Wilson current mirror and a Wilson mirror with its intrinsic external feedback removed are used to study external negative feedback effects under the influence of laser-induced single events. The measurement data clearly show notable improvements in SET response that can be made by employing both internal and external negative feedback. The peak transient in the output current is reduced, and the settling time upon a laser strike is shortened significantly by negative feedback. All four investigated current mirrors were fabricated with IBM 8HP 130 nm SiGe BiCMOS technology. [ABSTRACT FROM PUBLISHER]

This paper uses a physics-based TCAD degradation model to examine the accumulated stress damage of SiGe HBTs under pseudodynamic mixed-mode stress as a function of both electrical stress bias and temperature. The temperature dependence of mixed-mode stress damage is fully explored, beginning with impact-ionization calibration, and then by identifying and calibrating the dependence of scattering length and hydrogen diffusion parameters of the degradation model. After calibrating the model across electrical bias and temperature, the effectiveness and limitations of accumulated stress damage while varying electrical bias and while varying temperature are identified, and the implications of this aging model for circuit designers are discussed. [ABSTRACT FROM PUBLISHER]