1. Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic.
- Author
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Akarvardar, Kerem, Eggimann, Christoph, Tsamados, Dimitrios, Yogesh Singh Chauhan, Wan, Gordon C., Ionescu, Adrian Mihai, Howe, Roger T., and Philip Wong, H.-S.
- Subjects
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LOGIC circuits , *COMPUTER circuits , *TRANSISTOR circuits , *TRANSISTOR amplifiers , *DIGITAL electronics , *INTERFACE circuits , *ELECTRONIC circuits , *SWITCHING circuits , *METAL oxide semiconductor field-effect transistors - Abstract
An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and the stable travel range as a function of the structural parameters. Gate position is explicitly expressed as a function of the gate voltage, thus enabling the convenient integration of the analytical SGFET relationships into the standard MOSFET models. Starting from the new SGFET model, the influence of the mechanical hysteresis on the circuit steady-state behavior is discussed, the potential of using the SGFET as an ultra-low power switch is demonstrated, and the operation of the complementary SGFET inverter is analyzed. [ABSTRACT FROM AUTHOR]
- Published
- 2008
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