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Diagnosing multi-stage diseases typically requires doctors to consider multiple data sources, including clinical symptoms, physical signs, biochemical test results, imaging findings, pathological examination data, and even genetic data. When applying machine learning modeling to predict and diagnose multi-stage diseases, several challenges need to be addressed. Firstly, the model needs to handle multimodal data, as the data used by doctors for diagnosis includes image data, natural language data, and structured data. Secondly, privacy of patients' data needs to be protected, as these data contain the most sensitive and private information. Lastly, considering the practicality of the model, the computational requirements should not be too high. To address these challenges, this paper proposes a privacy-preserving federated deep learning diagnostic method for multi-stage diseases. This method improves the forward and backward propagation processes of deep neural network modeling algorithms and introduces a homomorphic encryption step to design a federated modeling algorithm without the need for an arbiter. It also utilizes dedicated integrated circuits to implement the hardware Paillier algorithm, providing accelerated support for homomorphic encryption in modeling. Finally, this paper designs and conducts experiments to evaluate the proposed solution. The experimental results show that in privacy-preserving federated deep learning diagnostic modeling, the method in this paper achieves the same modeling performance as ordinary modeling without privacy protection, and has higher modeling speed compared to similar algorithms. [ABSTRACT FROM AUTHOR]

This paper proposes the high speed low power analysis of 12 transistors 2x4 Low Power (LP) and Low Power Inverting (LPI) Decoders by using Dual Value Logic (DVL) and Complementary Metal Oxide Semiconductor (CMOS) Logic. A huge challenge faced by this era of developing is power reduction. The LP circuit design is a requesting issue in high performance digital frameworks, for example, microchips, DSPs and other different applications. Power and speed are the main highlights considered while comparing any design. Diminishing chip area is additionally truly impressive factor, designers need to recall when suggesting any novel design. 2x4 LP and LPI Decoders using 12T (Transistor) is used for conversion of binary inputs to associated output bits in a pattern. A novel design (CMOS logic and DVL logic) of 2x4 LP and LPI Decoders using 12T is proposed with area optimization, LP and high speed in this paper. Delay and power is evaluated between the novel design and CMOS logic. The novel design of 12T LP and LPI 2x4 Decoders is 60.72% optimized for power in contrast to CMOS logic design at a typical value of 1.8V. The proposed method has been validated using Cadence 45 GPDK (Generic Product Design Key) Virtuoso Tool. [ABSTRACT FROM AUTHOR]

We propose a technique for the wafer-level testing of the gate dielectrics of metal–insulator–semiconductor (MIS) devices by the high-field injection of electrons into the dielectric using a mode of increasing injection current density up to a set level. This method provides the capability to control a change in the charge state of the gate dielectric during all the testing. The proposed technique makes it possible to assess the integrity of the thin dielectric and at the same time to control the charge effects of its degradation. The method in particular can be used for manufacturing processes to control integrated circuits (ICs) based on MIS structures. In the paper, we propose an advanced algorithm of the Bounded J-Ramp testing of the gate dielectric and receive its approval when monitoring the quality of the gate dielectrics of production-manufactured MIS devices. We found that the maximum value of positive charge obtained when tested by the proposed method was a value close to that obtained when the charge was injected into the dielectric under a constant current with a Bounded J value despite large differences in the rate of degradation of the dielectric. [ABSTRACT FROM AUTHOR]

With the development of electronic technology, semiconductor memory is gradually shifting toward smaller area with less power consumption. SOT-MRAM is one of the competitive substitutes for DRAM and SRAM due to its superior endurance and switching speed. In contrast to STT-MRAM, the separation of read and write routes allows SOT-MRAM to have a lower error rate and higher lifetime, but this comes at the expense of the memory density. In recent years, vertical integrated circuits have relied on TSV to complete 3D stacking to ease the pressure of Moore's Law on scaling circuits. SOT-MRAM can take advantage of 3D stacking to reduce power and latency. More importantly, the density of SOT-MRAM can be improved at the same time. In the paper, simulation is conducted based on DESTINY, with the TSV model supplemented to NVSIM to evaluate the performance of MRAM 3D structures. The 3D SOT-MRAM structure in DESTINY can be implemented with a bus layer and interconnect structure between layers, which greatly reduces the expense of area. However, the 3D structure requires a more complex interconnect structure to truly meet the requirements of high density. For this reason, 3D model of unit interconnection using TSV is presented in the paper. Memory has several components, of which the memory array is the one with the largest area share. This paper explores the spatial structure of the array and proposes a new model which allows more complex interconnect structures to be accomplished on the same area. [ABSTRACT FROM AUTHOR]

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8–4.3%. This demonstrated the accuracy and effectiveness of the method we propose. [ABSTRACT FROM AUTHOR]

Deterministic lateral displacement (DLD) is a passive separation method that separates particles by hydrodynamic size. This label-free method is a promising technique for cell separation because of its high size resolution and insensitivity to flow rate. Development of capillary-driven microfluidic technologies allows microfluidic devices to be operated without any external power for fluid pumping, lowering their total cost and complexity. Herein, we develop and test a DLD-based particle and cell sorting method that is driven entirely by capillary pressure. We show microchip self-filling, flow focusing, flow stability, and capture of separated particles. We achieve separation efficiency of 92% for particle–particle separation and more than 99% efficiency for cell–particle separation. The high performance of driven flow and separation along with simplicity of the operation and setup make it a valuable candidate for point-of-care devices. [ABSTRACT FROM AUTHOR]

This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized $3\times 3$ window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained. [ABSTRACT FROM AUTHOR]

As the integration of chips in 3D integrated circuits (ICs) increases and the size of micro-bumps reduces, issues with the reliability of service due to electromigration and thermomigration are becoming more prevalent. In the practical application of solder joints, an increase in the grain size of intermetallic compounds (IMCs) has been observed during the reflow process. This phenomenon results in an increased thickness of the IMC layer, accompanied by a proportional increase in the volume of the IMC layer within the joint. The brittle nature of IMC renders it susceptible to excessive growth in small-sized joints, which has the potential to negatively impact the reliability of the welded joint. It is therefore of the utmost importance to regulate the formation and growth of IMCs. The following paper presents the electrodeposition of a Ni-W layer on a Cu substrate, forming a barrier layer. Subsequently, the barrier properties between the Sn/Cu reactive couples were subjected to a comprehensive and systematic investigation. The study indicates that the Ni-W layer has the capacity to impede the diffusion of Sn atoms into Cu. Furthermore, the Ni-W layer is a viable diffusion barrier at the Sn/Cu interface. The "bright layer" Ni2WSn4 can be observed in all Ni-W coatings during the soldering reflow process, and its growth was almost linear. The structure of the Ni-W layer is such that it reduces the barrier properties that would otherwise be inherent to it. This is due to the "bright layer" Ni2WSn4 that covers the original Ni-W barrier layer. At a temperature of 300 °C for a duration of 600 s, the Ni-W barrier layer loses its blocking function. Once the "bright layer" Ni2WSn4 has completely covered the original Ni-W barrier layer, the diffusion activation energy for Sn diffusion into the Cu substrate side will be significantly reduced, particularly in areas where the distortion energy is concentrated due to electroplating tension. Both the "bright layer" Ni2WSn4 and Sn will grow rapidly, with the formation of Cu-Sn intermetallic compounds (IMCs). At temperatures of 250 °C, the growth of Ni3Sn4-based IMCs is controlled by grain boundaries. Conversely, the growth of the Ni2WSn4 layer (consumption of Ni-W layer) is influenced by a combination of grain boundary diffusion and bulk diffusion. At temperatures of 275 °C and 300 °C, the growth of Ni3Sn4-based IMCs and the Ni2WSn4 layer (consumption of Ni-W layer) are both controlled by grain boundaries. The findings of this study can inform the theoretical design of solder joints with barrier layers as well as the selection of Ni-W diffusion barrier layers for use in different soldering processes. This can, in turn, enhance the reliability of microelectronic devices, offering significant theoretical and practical value. [ABSTRACT FROM AUTHOR]

Recently, a great deal of interest has been focused on developing sensors that can measure both pressure and light. However, traditional sensors are difficult to integrate into silicon (Si)-based integrated circuits. Therefore, it is particularly important to design a sensor that operates on a new principle. In this paper, junction piezotronic transistor (JPT) arrays based on zinc oxide (ZnO) nanowire are demonstrated. And the JPT arrays show high spatial resolution pressure and light mapping with 195 dpi. Because ZnO nanowires are arranged vertically above the p-type Si channel's center of the transistor, the width of the heterojunction depletion region is constricted by the positive piezoelectric potential generated by strained ZnO. In addition, photogenerated charge carriers can be created in the Si channel when JPT is stimulated by light, which increases its electrical conductivity. Consequently, the external pressure and light distribution information can be obtained from the variation in the output current of the device. The prepared JPT arrays can be compatible with Si transistors, which make them highly competitive and make it possible to incorporate both pressure and light sensors into large integrated circuits. This work will contribute to many applications, such as intelligent clothing, human–computer interaction, and electronic skin. [ABSTRACT FROM AUTHOR]

Designing efficient narrow-band near-infrared photodetectors integrated on silicon for telecommunications remains a significant challenge in silicon photonics. This paper proposes a novel silicon-based hot-electron photodetector employing Tamm plasmons (Si-based TP-HE PD) for narrow-band near-infrared photodetection. The device combines a one-dimensional photonic crystal (1DPC) structure, an Au layer, and a silicon substrate with a back electrode. Simulation results show that the absorption of the TP device with a back electrode is 1.5 times higher than without a back electrode, due to increased absorption from multiple reflections between the back electrode and the 1DPC structure. Experimentally, the responsivity of the fabricated device reaches 0.195 mA/W at a wavelength of 1400 nm. A phenomenological model was developed to analyze the photoelectric conversion mechanism, revealing reasonable agreement between the theoretically calculated and experimentally measured internal quantum efficiencies. Additional experiments and simulations demonstrate the tunability of the resonance wavelength from 1200 nm to 1700 nm by adjusting structural parameters. The Si-based TP-HE PD shows potential for silicon-based optoelectronic applications, offering the advantages of a simple structure, low cost, and compatibility with silicon photonic integrated circuits. This work represents the first demonstration of a silicon-based hot electron NIR photodetector utilizing Tamm plasmons. [ABSTRACT FROM AUTHOR]

The ever-increasing demand for high-speed data transmission in telecommunications and data centers has driven the development of advanced on-chip integrated electro-optic modulators. Silicon modulators, constrained by the relatively weak carrier dispersion effect, face challenges in meeting the stringent requirements of next-generation photonic integrated circuits. Consequently, there has been a growing interest in Pockels effect-based electro-optic modulators, leveraging ferroelectric materials like LiNbO3, BaTiO3, PZT, and LaTiO3. Attributed to the large first-order electro-optic coefficient, researchers have delved into developing modulators with expansive bandwidth, low power consumption, compact size, and linear response. This paper reviews the working principles, fabrication techniques, integration schemes, and recent highlights in Pockels effect-based modulators. [ABSTRACT FROM AUTHOR]

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore's era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented. [ABSTRACT FROM AUTHOR]

This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node. [ABSTRACT FROM AUTHOR]

Silicon photonic waveguide resonators, such as microring resonators, photonic crystal waveguide cavities, and Fabry–Perot resonators based on the distributed Bragg reflectors, are key device components for silicon-based photonic integrated circuits (Si-PIC). For the Si-PIC with high integration density, the device footprints of the conventional photonic waveguide resonators need to be more compact. Inverse design, which is operated by the design expectation and different from the conventional design methods, has been investigated for reducing the photonic device components nowadays. In this paper, we inversely designed the silicon photonic waveguide reflectors for two target wavelengths: one is 1310 nm and the other is 1550 nm. The silicon photonic waveguide reflectors have reflectance of 0.99993 and 0.9955 for the wavelength of 1310 nm and 1550 nm each with 5-μm-long reflectors. Also, we theoretically investigated Fabry–Perot resonators based on the inversely designed photonic waveguide reflectors. Q factors of the Fabry–Perot resonators have been calculated to be 1.3 × 105 for the wavelength of 1310 nm and 2583 for the wavelength of 1550 nm. We have expected that the inversely designed photonic waveguide reflectors and their applications for the Fabry–Perot resonators can be utilized for compact passive/active device components such as wavelength filters, modulators, and external cavity lasers. [ABSTRACT FROM AUTHOR]

Optical power splitters (OPSs) are utilized extensively in integrated photonic circuits, drawing significant interest in research on power splitters with adjustable splitting ratios. This paper introduces a compact, low-loss 1 × 2 asymmetric multimode interferometric (MMI) optical power splitter on a silicon-on-insulator (SOI) platform. The device is simulated using the finite difference method (FDM) and eigenmode expansion solver (EME). It is possible to attain various output power splitting ratios by making the geometry of the MMI central section asymmetric relative to the propagation axis. Six distinct optical power splitters are designed with unconventional splitting ratios in this paper, which substantiates that the device can achieve any power splitter ratios (PSRs) in the range of 95:5 to 50:50. The dimensions of the multimode section were established at 2.9 × (9.5–10.9) μm. Simulation results show a range of unique advantages of the device, including a low extra loss of less than 0.4 dB, good fabrication tolerance, and power splitting ratio fluctuation below 3% across the 1500 nm to 1600 nm wavelength span. [ABSTRACT FROM AUTHOR]

This paper is devoted to the study of CMOS IC parameter degradation during reliability testing. The paper presents a review of literature data on the issue of the reliability of semiconductor devices and integrated circuits and the types of failures leading to the degradation of IC parameters. It describes the tests carried out on the reliability of controlled parameters of integrated circuit TPS54332, such as quiescent current, quiescent current in standby mode, resistance of the open key, and instability of the set output voltage in the whole range of input voltages and in the whole range of load currents. The calculated values of activation energies and acceleration coefficients for different test temperature regimes are given. As a result of the work done, sample rejection tests have been carried out on the TPS54332 IC under study. Experimental fail-safe tests were carried out, with subsequent analysis of the chip samples by the controlled parameter quiescent current. On the basis of the obtained experimental values, the values of activation energy and acceleration coefficient at different temperature regimes were calculated. The dependencies of activation energy and acceleration coefficient on temperature were plotted, which show that activation energy linearly increases with increasing temperature, while the acceleration coefficient, on the contrary, decreases. It was also found that the value of the calculated activation energy of the chip is 0.1 eV less than the standard value of the activation energy. [ABSTRACT FROM AUTHOR]

In integrated circuit (IC) design, floorplanning is an important stage in obtaining the floorplan of the circuit to be designed. Floorplanning determines the performance, size, yield, and reliability of very large-scale integration circuit (VLSI) ICs. The results obtained in this step are necessary for the subsequent continuous processes of chip design. From a computational perspective, VLSI floorplanning is an NP-hard problem, making it difficult to be efficiently solved by classical optimization techniques. In this paper, we propose a deep reinforcement learning floorplanning algorithm based on sequence pairs (SP) to address the placement problem. Reinforcement learning utilizes an agent to explore the search space in sequence pairs to find the optimal solution. Experimental results on the international standard test circuit benchmarks, MCNC and GSRC, demonstrate that the proposed deep reinforcement learning floorplanning algorithm based on sequence pairs can produce a superior solution. [ABSTRACT FROM AUTHOR]

Self-destructing chips have promising applications for securing data. This paper proposes a new concept of energetic diodes for the first time, which can be used for self-destructive chips. A simple two-step electrochemical deposition method is used to prepare ZnO/CuO/Al energetic diode, in which N-type ZnO and P-type CuO are constricted to a PN junction. This paper comprehensively discusses the material properties, morphology, semiconductor characteristics, and exploding performances of the energetic diode. Experimental results show that the energetic diode has typical rectification with a turn-on voltage of about 1.78 V and a reverse leakage current of about 3 x 10-4 A. When a constant voltage of 70 V loads to the energetic diode in the forward direction for about 0.14 s or 55 V loads in the reverse direction for about 0.17 s, the loaded power can excite the energetic diode exploding and the current rises to about 100 A. Due to the unique performance of the energetic diode, it has a double function of rectification and explosion. The energetic diode can be used as a logic element in the normal chip to complete the regular operation, and it can release energy to destroy the chip accurately. [ABSTRACT FROM AUTHOR]

Although Moore's Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)..., longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor. [ABSTRACT FROM AUTHOR]

This paper presents the design of an integrated temperature sensor. The sensor was manufactured using the 3 µm CMOS technology. The proportional to absolute temperature sensor output signal was produced by two MOS transistors with biasing and buffering circuits. The sensor output voltage was linearly proportional to the absolute temperature in a wide range of temperature values. The measurement results coincide very well with the results of the process corner analysis. Certain non-linearities occurring at high temperature values are investigated in this paper in more detail. Additionally, the influence of neighboring circuits present in the manufactured integrated circuit on the sensor temperature response is studied. [ABSTRACT FROM AUTHOR]

Integrated circuits are being more and more extensively applied, and the reliability issues of devices are receiving increased attention from researchers. The study of electronic device performance is not limited to the device themselves; these studies also need to consider the operating environment, such as high temperature or high humidity, which requires fluid simulation. However, this approach inevitably increases the complexity of modeling and the difficulty of the equations to be solved. Aiming at the simulation of the thermal performance of a device under coupled humid air conditions, this paper proposes a surrogate model to quickly evaluate the multiphysical effects of humid air and a multiphysical solver based on it. In this research, the finite element method (FEM) is utilized to simulate the multiphysical problem, and the proposed method is verified as being efficient. [ABSTRACT FROM AUTHOR]

Bonding distance is defined by the projected distance on a substrate plane between two solder points of a bonding wire, which can directly affect the morphology of the bonding wire and the performance between internal components of the chip. For the inspection of the bonding distance, it is necessary to accurately recognize gold wires and solder points within the complex imagery of the chip. However, bonding wires at arbitrary angles and small-sized solder points are densely distributed across the complex background of bonding images. These characteristics pose challenges for conventional image detection and deep learning methods to effectively recognize and measure the bonding distances. In this paper, we present a novel method to measure bonding distance using a hierarchical measurement structure. First, we employ an image acquisition device to capture surface images of integrated circuits and use multi-layer convolution to coarsely locate the bonding region and remove redundant background. Second, we apply a multi-branch wire bonding inspection network for detecting bonding spots and segmenting gold wire. This network includes a fine location branch that utilizes low-level features to enhance detection accuracy for small bonding spots and a gold wire segmentation branch that incorporates an edge branch to effectively extract edge information. Finally, we use the bonding distance measurement module to develop four types of gold wire distribution models for bonding spot matching. Together, these modules create a fully automated method for measuring bonding distances in integrated circuits. The effectiveness of the proposed modules and overall framework has been validated through comprehensive experiments. [ABSTRACT FROM AUTHOR]

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization. [ABSTRACT FROM AUTHOR]

A novel inductance simulation circuit employing only two dual‐output voltage‐differencing buffered amplifiers (DO‐VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor‐less realization that provides electronically controllable realized inductance through biasing quantities of DO‐VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO‐VDBAs and does not exhibit instability at high frequencies. The simple and compact metal‐oxide semiconductor (MOS) implementation of the DO‐VDBAs (eight MOS per DO‐VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on‐chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF‐356. [ABSTRACT FROM AUTHOR]

At present, the ZPW-2000 integrated track circuits with the same standard as those used in the sections are widely used in China's high-speed railway stations, and the platform tracks in some stations adopt one-section track circuits. When the train is received at the station, the sending end of the track circuit of the platform track will face the train and send codes to provide trackside information for the train. If the train comes to a complete stop at the station and changes its direction by activating the cab on the intended end, when the starting signal is not at clear, the train may mistakenly receive the information sent by the track circuit of the adjacent line, and the train will depart from the station incorrectly, resulting in safety problems. In this paper, the method of adding an external relay circuit is proposed, and the timing of the train entering and leaving the platform track is determined by the circuit logic, and the concrete measure for applying train tail complementary code is provided, so that the double-end code sending can be realized after the train enters the track to solve the aforementioned problems. This solution only adds a small number of relays indoors, has no outdoor workload, does not need to change the train control software, and can be adapted to suit individual platform tracks of the station. The adaptation process is easy to implement and has minimal impact on transportation. This scheme can provide reference for the solution of safety protection enhancement for platform tracks equipped with integrated track circuits in high-speed railway stations. [ABSTRACT FROM AUTHOR]

It is explained, in introduction of this paper, why the description of the output signal at an A/D converter in the form that is presented in such respected textbooks as: a one written by Prandoni and Vetterli, and another one by van de Plassche is appropriate and correct. Unlike all others, especially those using in it the so-called comb of Dirac deltas. The latter ones do not lead to getting a correct formula for the spectrum of the output waveform of an A/D converter, or they yield no formula at all. Using the description of the A/D output signal in form of a step function (as in the textbooks mentioned above), a new, correct formula for calculating the spectrum of the sampled signal is derived in this paper. It is a revised version of the formula currently used in the literature, that is of the so-called Discrete-Time Fourier Transform (DTFT), and it is a product of this DTFT and a certain correction factor. Finally, some literature items are referred to in which the designers of integrated circuits (containing A/D converters) point out discrepancies that arise in designs when the multiplying factor mentioned above is not taken into account. [ABSTRACT FROM AUTHOR]

An improved combined-mode power converter (CMPC) for a solar photovoltaic (SPV) system is presented in this paper. Ten-power electronic switches are utilised for the functioning of the converter. The proposed converter has four modes of operation: buck, boost, inverter, and mixed mode. The new CMPC topology provides a unique and complex switching sequence for implementing the mixed-mode operation. This work uses a field-programmable gate array (FPGA) for mode selection and to create PWM (MS-PWM) signals. A digital MS-PWM controller is configured to switch between improved stepped perturb and observe (ISPO) maximum-power point tracking (MPPT) and sine wave PWM (SPWM). The ISPO provides the appropriate duty cycle for buck/boost operation, while the SPWM controls the inverter operation. This work's new digital PWM control algorithm supports mode selection, PWM generation, and reconfiguring PWM generation timings. The whole framework for constructing the MS-PWM controller employs a very high-speed integrated circuit hardware description language (VHDL). Simulation and experimental results are presented, proving that the digital MS-PWM controller uses fewer resources with improved accuracy. [ABSTRACT FROM AUTHOR]

This paper presents a novel multiple-input and multiple-output current-mode universal analog filter with electronic tuning capability. The proposed circuit uses a single second-generation current-controlled current conveyor with extra-X terminals (EX-CCCII) and two grounded capacitors. The filter can offer five standard filtering functions, namely low-pass, high-pass, band-pass, band-stop, all-pass responses, in the same circuit without changing the internal configuration of the filter by selecting appropriate input and output signals. To obtain the five standard filtering functions, inverted input signal and input matching conditions are absent. The natural frequency of all filter responses can be electronically controlled. The proposed circuit was simulated by SPICE using 0.18 μm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC). The results of experiments using the integrated circuit operational amplifier AD844 confirm the functionality of the new filter. [ABSTRACT FROM AUTHOR]

A capacitance multiplier is an active circuit designed specifically to increase the capacitance of a passive capacitor to a significantly higher capacitance level. In this paper, the use of a voltage differencing differential difference amplifier (VDDDA), an electronically controllable active device for designing grounded and floating capacitance multipliers, is proposed. The capacitance multipliers proposed in this study are extremely simple and consist of a VDDDA, a resistor, and a capacitor. The multiplication factor ( K c ) can be electronically controlled by adjusting the external bias current ( I B ). It offers an easy way of controlling it by utilizing a microcontroller for modern analog signal processing systems. The multiplication factor has the potential to be adjusted to a value that is either less than or greater than one, hence widening the variety of uses. The grounded capacitance multiplier can be easily transformed into a floating one by utilizing Zc-VDDDA. PSpice simulation and experimentation with a VDDDA realized from commercially available integrated circuits were used to test the performance of the proposed capacitance multipliers. The multiplication factor is electronically adjustable, ranging in approximation from 0.56 to 13.94. The operating frequency range is approximately three frequency decades. The realization of the lagging and leading phase shifters using the proposed capacitance multiplier is also examined and proven. The results reveal that the lagging and leading phase shifts are electronically tuned via the multiplication factor of the proposed capacitance multipliers. [ABSTRACT FROM AUTHOR]

A new method for estimating the parasitic emission of integrated circuits (ICs) is the main objective of this paper. In this study, experimental circuits were formulated, and printed circuit boards were fabricated to evaluate the input impedance at the power supply terminal of the designated microcontroller. Following the measurement of S-parameters for the experimental setup across a frequency spectrum ranging from 10 MHz to 2 GHz, Z-parameters were derived from the acquired S-parameter data. Then, all the unwanted impedance effects on the conducted line have been deleted mathematically with the de-embedding technique. The passive Resistor Inductor Capacitor (RLC) circuit was extracted using both analytic and modified genetic algorithms. Subsequently, the internal current values of the power supply pins were determined. Afterwards the passive RLC circuit and internal current values were obtained; the magnetic field in the internal structure of the IC was modeled as uniformly distributed conductive lines. The locations of the uniformly distributed conductive lines on the IC are defined as a straight route from the ends of the power supply pin to the IC core according to measurement results. A series of electromagnetic near-field measurements were conducted at varying frequencies in order to investigate the currents that traverse the power supply pins. The simulation of the magnetic field is conducted across the circuit under examination at varying frequencies and altitudes. The model results were compared to the measurement results obtained using the near-field test bench, which demonstrated a high degree of correlation. [ABSTRACT FROM AUTHOR]

Wafer-level three-dimensional stacked integration technology is demonstrated in this paper, employing three gallium arsenide (GaAs) monolithic integrated circuits (MMICs) and gold (Au) bumps, and specifically designed for high-density and low-profile applications operating at millimeter-wave frequencies. A ground coplanar waveguide to ground coplanar waveguide (GCPW to GCPW) hot via interconnect has been developed to facilitate vertical transitions within a multi-stacked electromagnetic (EM) environment. Electrical connection between the upper and lower layers is achieved through 70 µm-height Au bumps. Compared to 2.5D packaging, this innovative structure exhibits an increased integration capability of more than three times within the same area, with a thickness of 0.451 mm. Ultra-wideband transmission between RF chips is achieved within a compact area of 0.16 square millimeters, enabling extremely short-distance interconnect for system-in-package configurations. Appropriate utilization of ground metal within the package ensures strict electromagnetic field confinement, preventing interference from adjacent circuits. The designed transitions were fabricated and characterized. The measured result has an insertion loss of less than 0.65 dB and return loss of better than 20 dB up to 40 GHz for a back-to-back structure. This integration technology can further enhance integration capability, reduce transmission loss, and improve electromagnetic isolation. The presented approach holds significant potential for applications requiring high-density integration and reliable performance in the millimeter-wave regime. [ABSTRACT FROM AUTHOR]

During circuit conduction immunity simulation assessments, the existing black-box modeling methods for chips generally involve the use of time-domain-based modeling methods or ICIM-CI binary decision models, which can provide approximate immunity assessments but require a high number of tests to be performed when carrying out broadband immunity assessments, as well as having a long modeling time and demonstrating poor reproducibility and insufficient accuracy in capturing the complex electromagnetic response in the frequency domain. To address these issues, in this paper, we propose a novel frequency-domain broadband model (Sensi-Freq-Model) of IC conduction susceptibility that accurately quantifies the conduction immunity of components in the frequency domain and builds a model of the IC based on the quantized data. The method provides high fitting accuracy in the frequency domain, which significantly improves the accuracy of circuit broadband design. The generated model retains as much information within the frequency-domain broadband as possible and reduces the need to rebuild the model under changing electromagnetic environments, thereby enhancing the portability and repeatability of the model. The ability to reduce the modeling time of the chip greatly improves modeling efficiency and circuit design. The results of this study show that the "Sensi-Freq-Model" reduces the broadband modeling time by about 90% compared to the traditional ICIM-CI method and improves the normalized mean square error (NMSE) by 18.5 dB. [ABSTRACT FROM AUTHOR]

Matrix multiplication plays a crucial role in various engineering and scientific applications. Cannon's algorithm, executed within two-dimensional systolic arrays, significantly enhances computational efficiency through parallel processing. However, as the matrix size increases, reliability issues become more prominent. Although the previous work has proposed a fault-tolerant mechanism, it is only suitable for scenarios with a limited number of faulty processing elements (PEs). This paper introduces a pair-matching mechanism, assigning a fault-free PE as a proxy for each faulty PE to execute its tasks. Our fault-tolerant mechanism comprises two stages: in the first stage, each fault-free PE completes its designated computations; in the second stage, computations intended for each faulty PE are executed by its assigned fault-free PE proxy. The experimental results demonstrate that compared to the previous work, our approach not only significantly improves the fault tolerance of systolic arrays (applicable to scenarios with a higher number of faulty PEs) but also reduces circuit areas. Therefore, the proposed approach proves effective in practical applications. [ABSTRACT FROM AUTHOR]

Electrochemical measurements are vital to a wide range of applications such as air quality monitoring, biological testing, food industry, and more. Integrated circuits have been used to implement miniaturized and low-power electrochemical potentiostats that are suitable for wearable devices. However, employing modern integrated circuit technologies with low supply voltage precludes the utilization of electrochemical reactions that require a higher potential window. In this paper, we present a novel circuit architecture that utilizes dynamic voltage at the working electrode of an electrochemical cell to effectively enhance the supported voltage range compared to traditional designs, increasing the cell voltage range by 46% and 88% for positive and negative cell voltages, respectively. In return, this facilitates a wider range of bias voltages in an electrochemical cell, and, therefore, opens integrated microsystems to a broader class of electrochemical reactions. The circuit was implemented in 180 nm technology and consumes 2.047 mW of power. It supports a bias potential range of 1.1 V to −2.12 V and cell potential range of 2.41 V to −3.11 V that is nearly double the range in conventional designs. [ABSTRACT FROM AUTHOR]

Using DNA as the next-generation medium for data storage offers unparalleled advantages in terms of data density, storage duration, and power consumption as compared to existing data storage technologies. To meet the high-speed data writing requirements in DNA data storage, this paper proposes a novel design for an ultra-high-density and high-throughput DNA synthesis platform. The presented design mainly leverages two functional modules: a dynamic random-access memory (DRAM)-like integrated circuit (IC) responsible for electrode addressing and voltage supply, and the static droplet array (SDA)-based microfluidic structure to eliminate any reaction species diffusion concern in electrochemical DNA synthesis. Through theoretical analysis and simulation studies, we validate the effective addressing of 10 million electrodes and stable, adjustable voltage supply by the integrated circuit. We also demonstrate a reaction unit size down to 3.16 × 3.16 μm2, equivalent to 10 million/cm2, that can rapidly and stably generate static droplets at each site, effectively constraining proton diffusion. Finally, we conducted a synthesis cycle experiment by incorporating fluorescent beacons on a microfabricated electrode array to examine the feasibility of our design. [ABSTRACT FROM AUTHOR]

The 3D integrated circuit (3D-IC) is garnering significant attention from academia and industry as a key technology leading the post-Moore era, offering new levels of efficiency, power, performance, and form-factor advantages to the semiconductor industry. However, thermal management in 3D-ICs presents a critical challenge that must be overcome to ensure prosperity for this technology. Unlike traditional thermal management solutions that perceive heat generation in 3D-ICs negatively and aim to eliminate it, this paper proposes, for the first time, a thermal management method that positively utilizes heat to achieve low-power operation in 3D-ICs. This approach is based on a novel discovery that circuits can reduce power consumption at higher temperatures by leveraging the temperature effect inversion (TEI) phenomenon in ultralow-voltage (ULV) operating circuits, a characteristic of low-power techniques (TEI-LP techniques). Along with a detailed explanation of this discovery, this paper introduces new thermal management technologies for practical application in 3D-ICs. Furthermore, to achieve optimal energy efficiency with the proposed technology, we develop a temperature controller essential for this purpose. The developed controller is a deep learning-based PID autotuner. This paper proves the theoretical validity of the AI control algorithm designed for this purpose and demonstrates the functional correctness and power-saving effectiveness of the developed controller through intensively conducted simulations. [ABSTRACT FROM AUTHOR]

This paper reports a pioneering attempt at simultaneously analyzing gadolinium (Gd) distribution and surface imaging of surrogate debris samples with homogeneous and heterogeneous composition using a fiber-coupled acoustic wave-assisted microchip laser-induced breakdown spectroscopy (AW-mLIBS) system. This system must be applied to the remote analysis of fuel debris at the Fukushima Daiichi Nuclear Power Station (FDNPS). In the AW-mLIBS system, a microchip LIBS was used to measure the Gd distribution maps in the mixed oxide samples. Whereas, during elemental mapping by microchip LIBS, the laser-plasma acoustic waves were simultaneously recorded by microphone and applied for surface imaging of the samples. Additionally, the laser-plasma acoustic waves can be used to adjust the best-focusing position of the microchip LIBS because the acoustic wave amplitude is the strongest at the near best-focusing position. According to the measurement results, the emission spectra of the surrogate debris showed that the optical emission lines at 501.5 nm and 510.3 nm were suitable for Gd detection in the fuel debris sample. For Gd quantification, calibration curves were established from the intensity ratio of Gd/Ce emission lines, yielding the detection limits for Gd in the range of 0.04–0.09 wt% with a relative standard deviation of 3.9%. The surface imaging for the surrogate debris samples was successfully performed by collecting the laser-plasma acoustic waveforms during LIBS elemental mapping. [ABSTRACT FROM AUTHOR]

The development of cation electrokinetic concentrators (CECs) has been hindered by the lack of commercial anion-exchange membranes (AEMs). This paper introduces a γ-cyclodextrin-modified quaternized chitosan/polyvinyl alcohol (γ-CD/QCS/PVA) composite as an AEM, which is combined with a microchip to fabricate a CEC. Remarkably, the CEC only concentrates cationic species, thereby overcoming the interference of the highly abundant, negatively charged serum albumin in the blood sample. P-Glycoprotein (P-gp) is recognized as an efflux transporter protein that influences the pharmacokinetics (PK) of various compounds. The CEC was used to evaluate the activity of P-gp by detecting the positively charged rhodamine 123 (Rho123 is a classical substrate of P-gp) with no interference from serum albumin in the serum sample. Using the CEC, the enrichment factor (EF) of Rho123 exceeded 105-fold under DC voltage application. The minimal sample consumption of the CEC (<10 μL) enables reduction of animal sacrifice in animal experiments. Here, the CEC has been applied to evaluate the transport activity of P-gp in in vitro and in vivo experiments by detecting Rho123 in the presence of P-gp inhibitors or agonists. The results are in good agreement with those reported in previous reports. Therefore, the CEC presents a promising application potential, owing to its simple fabrication process, high sensitivity, minimal sample consumption, lack of interference from serum albumin and low cost. [ABSTRACT FROM AUTHOR]

Purpose: Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment. Design/methodology/approach: The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied. Findings: The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency. Originality/value: Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding. [ABSTRACT FROM AUTHOR]

A physical unclonable function (PUF) is a technology designed to safeguard sensitive information and ensure data security. PUFs generate unique responses for each challenge by leveraging random deviations in the physical microstructures of integrated circuits (ICs), making it incredibly difficult to replicate them. However, traditional silicon PUFs are now susceptible to various attacks, such as modeling attacks using conventional machine learning techniques and reverse engineering strategies. As a result, PUFs based on new materials or methods are being developed to enhance their security. However, in the realm of survey papers, it has come to our attention that there is a notable scarcity of comprehensive summaries and introductions concerning these emerging PUFs. To fill this gap, this article surveys PUFs based on novel technologies in the literature. In particular, we first provide an insightful overview of four types of PUFs that are rooted in advanced technologies: bionic optical PUF, biological PUF, PUF based on printed electronics (PE), and PUF based on memristors. Based on the overview, we further discuss the evaluation results of their performance based on specific metrics and conduct a comparative analysis of their performance. Despite significant progress in areas such as limited entry and regional expertise, it is worth noting that these PUFs still have room for improvement. Therefore, we have identified their potential shortcomings and areas that require further development. Moreover, we outline various applications of PUFs and propose our own future prospects for this technology. To sum up, this article contributes to the understanding of PUFs based on novel technologies by providing an in-depth analysis of their characteristics, performance evaluation, and potential improvements. It also sheds light on the wide range of applications for PUFs and presents enticing prospects for future advancements in this field. [ABSTRACT FROM AUTHOR]

Telecommand (TC) plays a crucial role in the success of high-altitude balloon experiments. Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are commonly employed to ensure reliable command operation. The Balloon Facility (BF) of Tata Institute of Fundamental Research (TIFR) uses a TC system based on BCH (31,16) coding technique, to control balloon and payload operations. This paper presents prototyping and implementation of TC encoder and decoder using Spartan 6 Field Programmable Gate Array (FPGA). The code is written in Very high-speed integrated circuit Hardware Description Language (VHDL). Simulation and synthesis are done using Xilinx ISE 14.7 design suite. Simulation results show the design is robust. The TC encoder is implemented in a commercial FPGA development board and the TC decoder is implemented in a specially designed FPGA board, successfully. This paper presents the salient features of the TC system in use and the implementation of the system using FPGA. [ABSTRACT FROM AUTHOR]

Summary: While wavelength division multiplexing (WDM) technology combines several wavelengths onto a single waveguide, the technology of mode division multiplexing (MDM) allows many orthogonal modes of the same wavelength to operate simultaneously without interchannel crosstalk. Thus, the hybrid WDM and MDM network in which the two above‐mentioned techniques cooperate could give a several‐fold increase in the overall network capacity. Constructing this network requires hybrid wavelength‐and‐mode multiplexers, especially ones with high integration and complementary metal‐oxide‐semiconductor (CMOS) compatibility. In this paper, we propose a design of a four‐mode triple‐band multiplexer that is capable of multiplexing up to 12 separate optical signal flows by utilizing four eigenmodes (TE0, TE1, TE2, and TE3) and three‐wavelength windows, which center at 1310, 1490, and 1550 nm. The device is on silicon‐on‐insulator (SOI) platform, consisting of four butterfly‐shaped multimode interference (MMI) couplers, four directional couplers, and a 4×1 cascaded asymmetric Y‐junction coupler. Via numerical simulations, the proposed design is verified to be able to operate effectively on the three aforementioned bandwidth slots with an optical conversion efficiency of over 93% in all functions. Moreover, it exhibits insertion loss less than 1.5 dB and crosstalk smaller than −16 dB within 25 nm bandwidth at each wavelength window. These results can affirm the success of wavelength–mode combination, which leads to a massive improve in the channel capacity on the same optical multiplexing system for optical telecommunications and photonics on‐chip interconnections. [ABSTRACT FROM AUTHOR]

Integrated photonics is demanded in applications operating at ultraviolet to visible wavelengths, such as atomic/quantum systems, on‐chip broadband receivers, and far‐field structured illumination autofluorescence microscopy. A fundamental challenge in these applications is efficient edge coupling from a single‐mode fiber (SMF) to on‐chip photonic components, which is critical for on‐chip integration. In this paper, a high‐efficiency edge coupler based on an alumina‐on‐insulator platform is introduced and experimentally validated. The coupler employs a symmetric double‐tip taper and a multimode interference (MMI)‐based optical combiner. The double‐tip taper effectively expands the mode field diameter at the chip facet to match that of the SMF at the initial stage. Then the MMI‐based combiner efficiently combines the two channels in the taper into a highly confined strip waveguide. A coupling loss of 2.85 dB/facet has been achieved for the transverse magnetic mode at the wavelength of 407 nm, which is the lowest insertion loss for fiber‐chip coupling on this platform to the best of the knowledge. The design can significantly reduce the insertion loss associated with fiber‐chip coupling, offering a key component for diverse areas ranging from atomic/quantum photonic integrated circuits and ultra‐high capacity communications to optical microscopes. [ABSTRACT FROM AUTHOR]

The logic circuit is the main component of an integrated circuit chip that dictates the operation and performance of the chip. The logic circuit based on a memristor can improve the integration and operation speed of the existing integrated circuit and reduce the chip size and the number of devices used by a single logic circuit. However, most of the research on logic circuits based on memristors has focused only on simulations, and research on the realization of logic circuits by hardware using actual memristors is limited. In this paper, a memristor based on graphene oxide with stable complementary resistive switching characteristics is fabricated, a logic circuit is built by using this device, and the logic functions of "IMP," "AND," and "NOR" are successfully realized. The complementary resistive switching device can alleviate the severe power loss caused by the memory separation of the von Neumann architecture. Moreover, its unique structure enables it to realize material logic independently without the use of multiple memristors and resistors, providing a new scheme for the physical realization of logic circuits. It also opens up a new path for integrated chips to break through von Neumann architecture. [ABSTRACT FROM AUTHOR]

With the continuous progress in integrated circuit technology, single-event effect (SEE) has become a key factor affecting the reliability of aerospace integrated circuits. Simulating fault injection using the computer simulation technique effectively reflects the SEE in aerospace integrated circuits. Due to various masking effects, only a small number of faults will result in errors; the traditional method of injecting one fault in one workload execution is inefficient. The method of injecting multiple faults in one workload execution will make it impossible to judge which fault results in errors because the propagation characteristic of SEE and faults may affect each other. This paper proposes an improved multi-point fault injection method to improve simulation efficiency and solve the problems of the general multi-point fault injection method. If one workload execution does not result in errors, multiple faults can be verified by one workload execution. If one workload execution results in errors, a specific grouping method can be used to determine which faults result in errors. The experimental results show that the proposed method achieves a good acceleration effect and significantly improves the simulation efficiency. [ABSTRACT FROM AUTHOR]

Purpose: This study aims to investigate the impact of government support on the coupling coordination degree of innovation chain and capital chain in integrated circuit (IC) enterprises and to explore the mechanism for considering talent in the influence path. Design/methodology/approach: This paper uses coupling coordination degree model to estimate the coupling of two chains, and applies dynamic panel system generalized method of moments (system-GMM) to analyze the impact of government support on coupling of two chains and conducts dynamic panel threshold regression to explore the threshold effect of talent in the influence of government support on coupling coordination degree. Findings: Serious imbalance in the coupling of two chains is a major obstacle in IC enterprises. Government support significantly reduces the coupling coordination degree. The talent in IC enterprises has a significant threshold effect. When the number of talent is lower than the threshold value, government support has a negative impact. Once the number of talent reaches a certain level, government support can significantly enhance the coupling of two chains. Compared with state-owned enterprises, government support has a greater negative impact on the coupling of the two chains in non-state-owned enterprises. The former needs more talent to take advantage of government support. Originality/value: This paper applies the concept of coupling into enterprises and deeply studies the coupling coordination degree of two chains. The influence mechanism of government support and talent on the coupling of two chains is explored, which reveals that government support cannot achieve the expected incentive effect without the support of talent. We also discuss the heterogeneous effect of government support and of talent in enterprises of different ownership types. [ABSTRACT FROM AUTHOR]

This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz. [ABSTRACT FROM AUTHOR]