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This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node. [ABSTRACT FROM AUTHOR]

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization. [ABSTRACT FROM AUTHOR]

The transformer is an important component of electrical engineering for many applications including those for integrated circuits. For integrated circuit applications, the use of a synthetic transformer has been recognised to be a viable option for a number of applications. This paper presents two new designs of electronically-controllable CMOS active transformers. The first preposition is based upon a capacitive T-network embedded between two active CMOS gyrators each of which has been obtained by a parallel back-to-back connection of one non-inverting and other inverting electronically-controllable CMOS transconductor. This circuit requires thirty-two MOSFETs, all operating in saturation region. The second design simulates an inductive T-network using two CMOS electronically-controllable floating inductors and one electronically-controllable CMOS grounded inductor thereby employing eighty MOSFETs. The first design offers the advantage of realising a step up as well as step down transformer by appropriate selections of the transconductances of two transconductors. The second design although uses a larger number of MOSFETs than the former but has the advantage of using three grounded capacitors which is a desirable from the view point of IC implementation. It may also be mentioned that using more MOSFETs does not increase layout area significantly since the capacitors require more layout area than all the MOSFETs put together. The workability of both the designs, along with their various performance characteristics and non-ideal analysis, has been well corroborated by computer simulations using SPICE software using 0.18 µm CMOS technology parameters. The application of the proposed circuits in the design of double tunned band pass filter has also been shown and its workability too has been validated by computer simulations using SPICE software. [ABSTRACT FROM AUTHOR]

Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (Vbk). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary. [ABSTRACT FROM AUTHOR]

Recently, interest in programmable photonics integrated circuits has grown as a potential hardware framework for deep neural networks, quantum computing, and field programmable arrays (FPGAs). However, these circuits are constrained by the limited tuning speed and large power consumption of the phase shifters used. In this paper, we introduce the memresonator, a metal-oxide memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter. These devices are capable of retention times of 12 hours, switching voltages lower than 5 V, and an endurance of 1000 switching cycles. Also, these memresonators have been switched using 300 ps long voltage pulses with a record low switching energy of 0.15 pJ. Furthermore, these memresonators are fabricated on a heterogeneous III-V-on-Si platform capable of integrating a rich family of active and passive optoelectronic devices directly on-chip to enable in-memory photonic computing and further advance the scalability of integrated photonic processors. Photonic integrated circuits have grown as potential hardware for neural networks and quantum computing, yet the tuning speed and large power consumption limited the application. Here, authors introduce the memresonator, a memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter to address these limitations. [ABSTRACT FROM AUTHOR]

Recently, interest in programmable photonics integrated circuits has grown as a potential hardware framework for deep neural networks, quantum computing, and field programmable arrays (FPGAs). However, these circuits are constrained by the limited tuning speed and large power consumption of the phase shifters used. In this paper, we introduce the memresonator, a metal-oxide memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter. These devices are capable of retention times of 12 hours, switching voltages lower than 5 V, and an endurance of 1000 switching cycles. Also, these memresonators have been switched using 300 ps long voltage pulses with a record low switching energy of 0.15 pJ. Furthermore, these memresonators are fabricated on a heterogeneous III-V-on-Si platform capable of integrating a rich family of active and passive optoelectronic devices directly on-chip to enable in-memory photonic computing and further advance the scalability of integrated photonic processors. Photonic integrated circuits have grown as potential hardware for neural networks and quantum computing, yet the tuning speed and large power consumption limited the application. Here, authors introduce the memresonator, a memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter to address these limitations. [ABSTRACT FROM AUTHOR]

Encryption chips are specialized integrated circuits that incorporate encryption algorithms for data encryption and decryption, ensuring data confidentiality and security. In China, the domestic SM4 algorithm is commonly utilized, as opposed to the international AES encryption algorithm. These widely implemented encryption standards have been proven to be difficult to crack through crypt analysis methods Currently, power consumption side-channel attacks are the most prevalent method. They involve capturing power consumption data during the encryption process and subsequently recovering the encryption key from this data. The two leading methods are Differential Power Analysis (DPA) and machine learning techniques. DPA does not necessitate prior knowledge but relies heavily on the number of power consumption curves. With only 50 power consumption data points, the accuracy is a mere 80%. Machine learning methods require prior knowledge, achieving an accuracy rate above 95% with only 30 power traces, albeit with training times typically exceeding 15 min. In this paper, a distributed energy analysis attack approach was presented based on Correlation Power Analysis (CPA). The power consumption data was divided into 16 subsets, with each subset corresponding to 8 bytes of the key. By training each subset separately, the 8-byte key's corresponding power consumption data is reduced to only 100 dimensions, resulting in a 76% decrease in cracking time and a 3% improvement in cracking accuracy rate.This article also trains a more complex 256 classification model to directly crack the final key, achieving a success rate of 28% in cracking 128-bit passwords with only 1 power trace [ABSTRACT FROM AUTHOR]

In this paper the design of power management integrated circuits for the energy harvesting of ultrasound waves in implanted biomedical devices is addressed. In particular, the paper focuses on the main building block of the power conversion stage which is represented by the AC/DC converter. After an in-depth analytical description of cross-coupled passive and active rectifiers, a detailed design procedure for the common-gate comparator is introduced. Then a comparison between the different discussed topologies is carried through simulation results using a 28-nm standard CMOS technology. The results provide useful design guidelines in choosing the best topology according to the design specifications. [ABSTRACT FROM AUTHOR]

The piezoelectric coupling principle is widely used (along with capacitive coupling and piezoresistive coupling) for MEMS accelerometers. Piezoelectric MEMS accelerometers are used primarily for vibration monitoring. Polymer piezoelectric MEMS accelerometers offer the merits of heavy-metal-free structure material and simple microfabrication flow. More importantly, polymeric piezoelectric MEMS accelerometers may be the basis of novel applications, such as fully organic inertial sensing microsystems using polymer sensors and organic integrated circuits. This paper presents a novel polymer piezoelectric MEMS accelerometer design using PVDF films. A simple and rapid microfabrication flow based on laser micromachining of thin films and 3D stereolithography was developed to fabricate three samples of this design. During proof-of-concept experiments, the design achieved a sensitivity of 21.82 pC/g (equivalent open-circuit voltage sensitivity: 126.32 mV/g), a 5% flat band of 58.5 Hz, and a noise density of 6.02 µg/√Hz. Thus, this design rivals state-of-the-art PZT-based counterparts in charge sensitivity and noise density, and it surpasses the performance capabilities of several commercial MEMS accelerometers. Moreover, this design has a 10-times smaller device area and a 4-times larger flat band than previous state-of-the-art organic piezoelectric MEMS accelerometers. These experimentally validated performance metrics demonstrate the promising application potential of the polymeric piezoelectric MEMS accelerometer design presented in this article. [ABSTRACT FROM AUTHOR]

This paper continues the research on the circuit synthesis problem for a multiplexer function of logic algebra, which is a component of many integrated circuits and is also used in theoretical study. The exact value of the depth of a multiplexer with select lines in the standard basis is found under the assumption that the conjunction and disjunction gates are of depth 1 and the negation gate is of depth 0; the depth equals if . Thus, it follows from previous results that the exact depth value equals for all positive integers such that either or . Moreover, for , this value equals 2, and for , it equals either or . Similar results are also obtained for a basis consisting of all elementary conjunctions and elementary disjunctions of two variables. [ABSTRACT FROM AUTHOR]

This paper reports the design and numerical results of three new extremely compact and efficient flat-top band-pass plasmonic filters operating in the near-infrared region. The proposed structures are realized in metal–insulator-metal plasmonic waveguides based on stub, tilted T-junction and right-angle trapezoid configurations. A built-in parameterized genetic algorithm is applied to maximize the transmission efficiency, while at the same time contributing to shrinking down the size of the device structures. It is shown that the tunability of the optical filters can be realized by modulating their structural parameters to gain control over the band-pass filtering wavelengths. Numerical calculations are conducted based on the finite element method of CST Microwave Studio and demonstrate that the suggested ultra-compact plasmonic waveguide filters offer wide bandwidths of more than 270 nm, 424 nm, and 289 nm, with transmission efficiencies of higher than 80%, 74.2%, and 74.3%, respectively. The sizes of the proposed wavelength filters are 490 nm × 575 nm, 350 nm × 180 nm, and 420 nm × 150 nm, respectively, which make them attractive candidates for applications in high density photonic integrated circuits (PICs). As a result, because of the promising characteristics of the proposed topologies such as their high efficiency, compact size, tunability, and simple structure they may find applications in on-chip integration, laser technology, and multi-photon fluorescence. [ABSTRACT FROM AUTHOR]

Silicon (Si) waveguide crossing serves as an enabling technology for dense Si photonic integrated circuits. Efficient crossing designs significantly boost the performance of photonic devices with many crossings. In this paper, several fundamental optical logic functions, such as XOR, AND, OR, NOT, NOR, NAND, and XNOR, are reported at 1550 nm telecom wavelength using direct Si waveguide crossing. The proposed scheme is made up of three input waveguides and one output waveguide arranged in the shape of the symbol ' + ' with a microring resonator in the middle. The operation of the specified logic functions depends on the constructive and destructive interferences generated by the phase differences between the incident optical beams. Using the contrast ratio and amplitude modulation metrics, the performance of the target logic operations is evaluated. Additionally, it is investigated and assessed how much the critical operating parameters affect the spectrum transmission. The proposed waveguide-based scheme can achieve better performance compared to other reported designs of similar nature, according to simulation outcomes derived using Lumerical FDTD. [ABSTRACT FROM AUTHOR]

In this paper, ultra-compact, high isolation-ratio optical isolators for use in wavelength-division multiplexing networks are presented. The isolator is composed of two parts, including a straight waveguide and a resonator. The performance of the isolator is investigated for two kinds of disk and ring resonators. The structure is based on the metal–insulator–metal configuration in which the metal parts are of gold and the insulator parts are of a magneto-optical material. The effecting parameters, including the dimensions of the disk/ring resonator, the gap between the waveguide and the resonator, and the waveguide material are comprehensively studied using the finite-difference time-domain method. By changing the geometrical variables and materials, the isolation ratio of the disk-and ring-based isolators can reach up to 33.47 dB and 29.06 dB, respectively. The footprint of both isolators is less than 1 μm2. The proposed isolators can be used in photonic integrated circuits due to their ultra-compact footprint, high isolation ratio, and CMOS-compatible structures. [ABSTRACT FROM AUTHOR]

This paper proposes a visual management scheme of medical things with a color-change radio frequency identification (RFID) tag. The color-change RFID tag employs a specific RFID tag integrated circuit (IC) and a laminated pH-indicating paper. The IC has energy harvesting and switched ground functions, which enable it to generate electricity to the laminated pH-indicating paper. This phenomenon causes electrolysis of NaCl solution absorbed in the laminated pH-indicating paper. Electrolysis generates alkaline matter to change the color of the pH-indicating paper. This paper gives a new and sensitive structure of the laminated pH-indicating paper. The proposed advanced color-change RFID tag with new laminated pH-indicating paper succeeds in changing its color noticeably at a 1 m distance using an RFID reader radiating 1 W radio waves. The color change was observed 3–5 s after starting radio wave irradiation. The results of this experiment also confirm that the changed color can be held for over 24 h. Furthermore, two demonstrations of the visual management system of medical things (patient clothes and sanitizers) are presented. [ABSTRACT FROM AUTHOR]

All-inkjet-printing of transistors has received much attention for low cost and flexible integrated circuits. However, most flexible field-effect transistors (FETs) based on the emerging two-dimensional materials suffer from the high cost of substrate and electrode materials. The requirements for high-temperature synthesis and precise control in processing add another layer of complexity. To overcome these issues, low-cost flexible paper-based MoS2 FETs were fabricated by inkjet printing of MoS2 channel materials on paper. Additionally, we proposed and achieved the mask-less and low-temperature formation of source and drain electrodes on paper using in-situ selective-area copper reduction. A low sub-threshold swing of 80 mV/dec, high on/off ratio of 105, and very high turn-on current (Ion) of 200 μA of the paper-based flexible MoS2 FETs were demonstrated using the proposed low-cost and facile all-inkjet-printing technique. The all-inkjet-printing technique assisted by in-situ copper reduction opens new opportunities for low-cost and batch fabrication of paper-based electronic devices in ambient conditions. [ABSTRACT FROM AUTHOR]

Research on artificial neural network computing based on conventional integrated circuit chips has made significant progress, but it faces technical bottlenecks such as reduced energy consumption, computing speed, and efficiency. So, it is seeking integrated chips based on optical interconnections to solve the current dilemma. Fortunately, the small size and very localized graphene surface plasmon waves offer the possibility of optical integrated chips. In this paper, we propose a graphene-based one-bit optical numerical comparator. The comparator is located on the top of a 0.4-μm2 rectangular dielectric layer, mainly consisting of Y-shaped graphene nanoribbons. The on/off effect of the graphene nanoribbons is achieved by applying an external voltage to change the chemical potential energy of the graphene switching bands. The proposed optical numerical comparator with 9.55-μm TM mode light achieves a minimum extinction ratio of 31.12 dB and amplitude modulation of 0.77 dB, as shown by the finite-difference time-domain (FDTD) method. Compared with the current optical numerical comparators, it has the advantages of a high extinction ratio, small size, low loss, and high stability. In addition, the effect of process deviation of graphene nanoribbons on the reliability of the designed optical numerical comparator is analyzed by simulation. It is beneficial to developing integrated photonic devices and has some significance for developing ultra-high-frequency and integrating artificial neural network computing. [ABSTRACT FROM AUTHOR]

Medical implants and portable wireless sensors are the most serious of biomedical applications due to the dependence on limited battery lifetime. Consequently, energy efficiency integrated circuits designs must be put to higher attention. A particular distinguishing contribution of this paper is its focus on the power consumption that affects battery life and the heat dissipated for biomedical applications. This paper demonstrates a power-efficient implementation of analog-to-digital converter (ADC) based on voltage-controlled oscillator (VCO) to convert the collected analog vital signs into digital data for digital signal processing. The current-starved scheme is employed to implement the VCO efficiently with five-stage which leads to high savings in power and area. D-flip flop (D-FF) scheme is proposed to simplify the hardware architecture of the proposed reset counter. The proposed architecture is implemented with 130 nm CMOS technology and it can perform conversion of analog input signal to digital output using a straightforward hardware structure. The proposed VCO-based ADC achieves improvement in energy saving. Simulation results confirm that this work attains a power dissipation of 0.257 mW and active area of 0.007 mm2, and a very good Walden FOMW of 125 dB. The proposed methodology can implement any number of bits of the ADC by using the appropriate voltage-controlled oscillator with the convenient reset counter. [ABSTRACT FROM AUTHOR]

This paper designs a novel E-plane waveguide magic-T in 220 GHz and develops a high-power solid-state power amplifier (SSPA) operating at 210–230 GHz in combination with eight InP high electron mobility transistor terahertz monolithic integrated circuits (TMICs). The 8-way divider-combiner network is composed of low-loss WR-4 novel E-plane waveguide magic-T. The matching load of waveguide magic-T is the air outside the waveguide module, which is connected to the pyramidal horn antenna of WR-4 waveguide to WR-10 waveguide. A monolithically integrated dipole-to-waveguide transition eliminates the need for wirebonding and additional substrates. The low-loss corporate power combining and low-loss dipole-to-waveguide transition achieve high-power combining efficiency of SSPA. The hydroxyl-iron is placed in the upper cavity of TMIC to prevent the cavity from resonance. The SSPA module demonstrated small-signal gain ≥ 10 dB from 210 to 229 GHz. The saturated output power was > 100 mW from 215 to 227 GHz and peak output power of 110 mW with 83% power combining efficiency at 220 GHz. [ABSTRACT FROM AUTHOR]

The dielectric loss of Cu with high thermal conductivity is large at high frequency, which cannot meet the performance requirements in high-integrated circuits. There is an urgent need for materials to reduce its dielectric loss. In this paper, the thermal conductivity and dielectric properties of the AlN coating-Cu substrate system were controlled by changing the N2 pressure. The results showed that the crystallinity of hcp-AlN in AlN coating increased significantly when the proportion of N2 pressure was increased. With the increase of the N2 pressure, the particle size on the surface and the roughness of the coating improved. The AlN coating prepared at high N2 pressure had high dielectric constant and low dielectric loss at high frequency compared to those of the coatings prepared at low N2 pressure. At the same time, the AlN coating prepared under high N2 pressure on the Cu substrate did not decrease the thermal conductivity of Cu substrate. The AlN-Cu system prepared in this paper had high thermal conductivity and good dielectric properties, providing theoretical guidance for integrated circuit packaging and capacitor applications. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

Many devices based on silicon and other photonic integrated circuit platforms exhibit significant polarization dependence. Polarization beam splitter (PBS) is a device that split optical signals into transverse electric (TE) and transverse magnetic (TM) modes. Among various PBSs, asymmetric directional couplers are widely used due to their fine performance, but their working bandwidth is limited due to wavelength changes that can lead to deviations in effective refractive index and coupling strength. We propose a PBS, which uses metamaterial anisotropy to replace structural asymmetry and break the bandwidth bottleneck. It achieves good performance in the wavelength range of 258 nm, where the extinction ratio of the TM polarization is greater than 24 dB and that of the TE polarization is greater than 26 dB. It covers the E, S, C, L, and U bands, and the coupling area is as small as 7.25×2.625 μm, with a total device footprint of 15.65×6.125 μm. [ABSTRACT FROM AUTHOR]

Multiwavelength nanophotonic devices are essential components in photonic integrated circuits for on-chip all-optical signal processing applications with enhanced data-storage capacity and increased bandwidth. Wavelength demultiplexing is a widely used photonic processing function, required for photonic signal processing on compact silicon chip designs. In this paper, we study optical rainbow trapping in a line defect photonic waveguide, and propose to use that effect for demultiplexing the light at visible spectrum. A defect waveguide is created in graded-index photonic crystal (GRIN PC) structure (the structure is composed of Si- PC cylinders having gradually varying radii along one dimension) as main channel, which allows the rainbow-trapping along the waveguiding channel. Vertical (side) channels are introduced to the system for efficient wavelength demultiplexing with low crosstalks and high coupling efficiencies thanks to the fact that incident light is localized at different positions along the main channel for certain operating visible wavelengths of The corresponding inter-channel cross-talks of is obtained at these incident wavelengths, which strengthens the idea of using such a GRIN PC structure for efficient wavelength demultiplexing applications. The studied multichannel demultiplexing device is relatively compact with a footprint of , which could be fabricated via simple lithography processes on a single Si- wafer. As far as authors' knowledge, this is the first time in literature that GRIN PC waveguide is implemented for multichannel wavelength demultiplexing function. The proposed GRIN PC design could be implemented for color sensitive photo-detection, absorption enhancement and optical spectroscopy. [ABSTRACT FROM AUTHOR]

This paper proposes a symmetric plasmonic bandpass filter topology based on metal–insulator-metal waveguide configuration. The proposed filter is numerically simulated using the finite difference time domain method. Silver and air have been used as metal and dielectric materials in the proposed structure, respectively. The model used to characterize silver is Johnson and Christy. By the introduction of nanorods to the filter structure, the transmittance value can be improved. As a result, a maximum transmission peak of 93% is obtained. Other advantages of the proposed plasmonic filter include having a high Q-factor, a bell-shaped transmission spectrum, and being single-mode. Therefore, the proposed plasmonic bandpass filter can potentially be used in photonic integrated circuits. [ABSTRACT FROM AUTHOR]

In integrated photonic circuits, microring resonators are essential building blocks but are susceptible to phase errors due to fabrication imperfections and optical power fluctuations. Conventional active phase tuning methods are power-intensive and challenging to integrate into densely packed photonic chips. This study proposes a solution by integrating a thin 2D layer of In4/3P2Se6 (InPSe) onto silicon microring resonators (Si-MRR). This approach mitigates sensitivity to laser power and achieves non-volatile wavelength trimming. Under bias voltage, the device exhibits electro-optic behavior, offering a non-volatile phase trimming rate of −2.62 pm/V to −4.62 pm/V, corresponding to InPSe thicknesses of 45 nm to 120 nm. Low optical losses of 0.0091 to 0.0361 dB/μm were also measured, corresponding to thicknesses of 30 nm to 120 nm. The devices demonstrate stable in-situ resonance wavelength stabilization and bidirectional trimming, ensuring cyclic stability for non-volatile phase control. This advancement enhances the performance of silicon photonics across diverse applications, facilitating high-capacity, high-power operation in compact designs. [ABSTRACT FROM AUTHOR]

Photonic integrated circuits have been extensively explored for optical processing with the aim of breaking the speed and energy efficiency bottlenecks of digital electronics. However, the input/output (IO) bottleneck remains one of the key barriers. Here we report a photonic iterative processor (PIP) for matrix-inversion-intensive applications. The direct reuse of inputted data in the optical domain unlocks the potential to break the IO bottleneck. We demonstrate notable IO advantages with a lossless PIP for real-valued matrix inversion and integral-differential equation solving, as well as a coherent PIP with optical loops integrated on-chip, enabling complex-valued computation and a net inversion time of 1.2 ns. Furthermore, we estimate at least an order of magnitude enhancement in IO efficiency of a PIP over photonic single-pass processors and the state-of-the-art electronic processors for reservoir training tasks and multiple-input and multiple-output (MIMO) precoding tasks, indicating the huge potential of PIP technology in practical applications. Integrated photonic iterative processors provide a novel I/O-efficient computing paradigm for matrix-inversion-intensive tasks, achieving higher speed and energy efficiency than state-of-the-art electronic and photonic processors. [ABSTRACT FROM AUTHOR]

Controlling large-scale many-body quantum systems at the level of single photons and single atomic systems is a central goal in quantum information science and technology. Intensive research and development has propelled foundry-based silicon-on-insulator photonic integrated circuits to a leading platform for large-scale optical control with individual mode programmability. However, integrating atomic quantum systems with single-emitter tunability remains an open challenge. Here, we overcome this barrier through the hybrid integration of multiple InAs/InP microchiplets containing high-brightness infrared semiconductor quantum dot single photon emitters into advanced silicon-on-insulator photonic integrated circuits fabricated in a 300 mm foundry process. With this platform, we achieve single-photon emission via resonance fluorescence and scalable emission wavelength tunability. The combined control of photonic and quantum systems opens the door to programmable quantum information processors manufactured in leading semiconductor foundries. Integrating tunable quantum emitters with commercial photonic circuits is promising for quantum information applications but remains a challenge. Here the authors report integration of InAs/InP microchiplets containing quantum dot single photon emitters into a large-scale foundry silicon platform. [ABSTRACT FROM AUTHOR]

Patterns on polymers usually have different mechanical properties as those of the substrates, causing deformation or distortion and even detachment of the patterns from the polymer substrates. Herein, we present a wrinkling strategy, which utilizes photolithography to define the area of stress distribution by light-induced physical crosslinking of polymers and controls diffusion of residual solvent to redistribute the stress and then offers the same material for patterns as substrate by thermal polymerization, providing uniform wrinkles without worrying about force relaxation. The strategy allows the recording and hiding of up to eight switchable images in one place that can be read by the naked eye without crosstalk, applying the wrinkled polymer for optical anti-counterfeiting. The wrinkled polyimide film was also utilized to act as a substrate for the creation of fine copper circuit by a full-additive process. It generates flexible integrated circuit (IC) carrier board with copper wire density of 400% higher than that of the state-of-the-art in industry while fulfilling the standards for industrialization. Current wrinkling processes for pattern formation cannot be easily controlled, resulting in deformation or detachment of patterns from substrates. Here, Zhong et al. report a wrinkling strategy for creating patterned structures with long-range order and resistant to force relaxation. [ABSTRACT FROM AUTHOR]

This work consists of a design and simulation of a structure composed by an aluminum structural layer whose purpose is to act as an angular electrostatic micromotor. The structure of the micromotor is defined using the layers available from a 0.5 μm CMOS technology used for integrated circuit fabrication. In this proposal, a digital circuit is configured for the generation of the three phases needed for proper operation of the micromotor. The phases and poles of the stator are biased in an alternating sequence, thus, when there is a potential difference between the misaligned poles of the rotor and stator, an electrostatic force is generated that causes the motor to advance one step. If this sequence is performed correctly and periodically, the rotor reaches a set speed in a clockwise direction. As a novel contribution to the presented design, an FGMOS transistor is used as an auxiliary element to measure the rotating speed of the micromotor and whose control gate is a structure mechanically coupled to the rotor. The elements of the system are proposed for being monolithically integrated: the rotation control circuit, the micromotor, and the speed sensor. This work also shows a static simulation and a time-dependent simulation that allows predicting the behavior over time and the torque generated by the micro-actuator. [ABSTRACT FROM AUTHOR]

Origami, an ancient form of papercraft, provides a way to develop functional structures for engineering applications. In this paper, we report an approach to design and manufacture a stretchable circuit board (SCB) with origami structures. The benefits of developable, flat-foldable, and rigid-foldable origami-based structures as SCBs are discussed, and a representative structure, Miura fold (or Miura-ori), is chosen to be investigated. Under the constraints induced by the mounted components' dimensions, the Miura-ori structures for specific applications can be defined. We propose three methods for better fabrication, including direct folding, stiffness modification, and kirigami enhancement, to improve a planar sheet's foldability. A wearable ECG (electrocardiogram) system based on MO-SCB (Miura-ori enabled SCB) technology is built, and the stretchable portion is made of commercial FPCBs (flexible printed circuit board), providing desired stretchability and reliability. The proposed technology routine is compatible with industrial production and may pave the application of stretchable electronics. [ABSTRACT FROM AUTHOR]

This paper presents a compact and efficient integrated interface circuit for piezoelectric energy harvesting. While state-of-the-art interface circuits require either an external inductor or a significant number of additional capacitors to achieve high voltage flip and thus improve power efficiency, the proposed Full Active Rectifier on Flipping Capacitor (FAR-FC) is based on a reduced set of flipping capacitors and an active rectifier to efficiently flip the voltage across the piezoelectric transducer. In addition, this optimized SSHC circuit reaches better power efficiency when the piezoelectric transducer operates under low mechanical excitation, i.e. when the open-circuit voltage of the piezoelectric transducer is V o c = 1 V , while usually V o c ≥ 2 V in literature. Furthermore, the FAR-FC supports piezoelectric transducers with higher inherent capacitance values compared to those usually reported in literature, which makes the circuit potentially suitable for a larger variety of applications. The interface circuit was designed and fabricated in a 0.35 μm CMOS process. Measurement results show that the voltage flip efficiency goes up to 90 % . It also reveals that the proposed FAR-FC circuit achieves power performance up to 5.64 × higher than a conventional full-bridge rectifier. [ABSTRACT FROM AUTHOR]

This paper presents the design and numerical investigation of tunable, ultra-compact, and highly-efficient plasmonic filters based on stepped impedance resonators (SIRs). The proposed devices are realized in metal–insulator-metal (MIM) plasmonic waveguide systems and exhibit more degrees of freedom and high flexibility to design resonator-based devices, thanks to the SIRs. The principle of conventional SIRs is discussed in terms of equivalent circuit model and characteristic impedance. Among the three proposed plasmonic filters, one of them acts as a short-wavelength, while the other two nanostructures work as long-wavelength cut-off filters at near-infrared region (NIR) and telecom wavelengths. Simulation results are carried out by a finite element method (FEM)-based solver and indicate that the cut-off wavelengths of the proposed resonators found to be at 1187 nm, 1265 nm, and 999 nm, respectively, can be easily tuned by modulating their structural parameters. In addition to the mentioned remarkable properties of the designed structures including the size which are found to be 500 nm × 310 nm, 350 nm × 285 nm, and 210 nm × 195 nm, respectively, the simple structures of the proposed topologies facilitate their fabrication process. Therefore, the suggested devices can contribute to the development of miniaturized, tunable, and efficient optical components for photonic integrated circuits (PICs) applications and in optical wireless communication systems. [ABSTRACT FROM AUTHOR]

In this paper, four individual structures based on graphene-plasmonic nano combinations are proposed for detection of corona viruses and especially COVID-19. The structures are arranged based on arrays in the shapes of half-sphere and one-dimensional photonic crystal formats. The half-sphere and plate shaped layers are made of Al, Au, SiO2 and graphene. The one-dimensional photonic crystals lead the wavelength and peak corresponding to the absorption peak to lower and higher amounts, respectively. In order to improve the functionality of the proposed structures, effects of structural parameters and chemical potentials are considered. A defect layer of GZO is positioned in the middle of one-dimensional photonic crystal layers to shift the absorption's peak wavelength to the appropriate wavelength range for diagnosing corona viruses (~300 nm to 600 nm). The last proposed structure is considered as a refractive bio-sensor for detection of corona viruses. In the final proposed structure (based on different layers of Al, Au, SiO2, GZO and graphene), corona viruses are considered as the biomolecule layer and the results are obtained. The proposed bio-sensor can be a good and functional candidate for detection of corona viruses and especially COVID-19 in photonic integrated circuits with the satisfying sensitivity of ~664.8 nm/RIU (refractive index unit). [ABSTRACT FROM AUTHOR]

The Internet of Things is gaining popularity throughout the world. With the growth of digital communication, healthcare 4.0 are being implemented by many businesses industry in order to establish a more resilient, competent, and intelligent smart healthcare system. Healthcare monitoring services are the part of smart healthcare system. These types of monitoring systems are mainly based on the Internet of Things (IoT). IoT helps to integrate multiple sensors and objects that can directly communicate with each other without human intervention. This type of IoT based systems are vulnerable to different adversarial threats such as cloning attack, impersonation attack etc. Hence medical IoT device authentication is essential in smart healthcare to verify user legitimacy. One way to verify user legitimacy is using physical unclonable function (PUF). The PUF protects sensor nodes from tampering, cloning attack. In this paper, we have proposed a lightweight PUF based authentication mechanism for embedded IoT devices in e-healthcare system. The proposed authentication technique helps to authenticate IoT sensor nodes which are responsible for transmitting sensitive health data in a health monitoring system. The performance comparison shows that the protocol is efficient with high through put and low computational load. The security analysis of the authentication scheme shows it would resist different types of network attacks. The proposed authentication provides a facility that no one except that the primary users can have access to the raw challenge response pair of integrated PUF circuits so that adversary will unable to build another same PUF model. Also the success probability is 2 - 76 for recovering the transformed 128 bit challenge and responses. [ABSTRACT FROM AUTHOR]

This paper proposes an inductor-less D-latch. In the proposed D-latch, negative feedback is used that makes input impedance appears to be inductive for the high-frequency input signal. The bandwidth is increased by around 23% due to this effect. Two applications are shown in this paper to verify the proposed latch operation: a pseudo-random binary sequence (PRBS) generator and a serializer. The speed of the PRBS generator and serializer has improved by 15.8% and 23% using the proposed latch, respectively. The post-layout simulation results in 90 nm CMOS technology with a power supply of 1 V prove the concept. To study functional correctness and scalability of the proposed architecture to lower technology nodes, 22 nm PTM model is used and verified the correct operation of the proposed architecture. [ABSTRACT FROM AUTHOR]

In this paper, a programmable low-power analog front-end (AFE) integrated circuit (IC) for biomedical signal monitoring systems is presented. The whole system includes four parts, instrumentation amplifiers (IA), programmable gain amplifiers (PGA), programmable bandwidth filters (PBF) and successive approximation register analog-to-digital convertors (SAR ADC). The proposed IA employs a pseudo-differential structure to enhance the input impedance of the system. A novel hybrid bandwidth extension technology is introduced in the proposed PGA to correct the low-frequency distortion and improve the low-frequency bandwidth. In the design of PBF, the current steering technology is applied to achieve an area-efficient and energy-efficient architecture. Furthermore, a novel efficient switching scheme and a self-calibration dynamic element matching method are presented in the design of SAR ADC to reduce the power consumption and eliminate the effect of capacitor mismatch. In 0.18 μm CMOS technology, this AFE IC consumes 46.8 μW and occupies 0.36 mm2. It achieves a variable gain from 40.4 to 55.1 dB under different modes designed for different biomedical signals. The spurious-free dynamic range and signal-to-noise plus distortion ratio of the proposed SAR ADC are 71.3 and 53.3 dB, respectively, along with a figure of merit of 0.18 pJ/conv. [ABSTRACT FROM AUTHOR]

In the present study, five nano logical gates have been designed by means of eight rectangular Kerr nonlinear resonators in a unique plasmonic structure. All the logical gates were simulated with a single nano plasmonic composition, capitalizing on the two-dimensional Finite-Difference-Time-Domain method. The results showed that, on average, the transmission differences for the AND, NOR, OR, NAND, and XOR gates were 98%, 99%, 200%, 94%, and 96%, respectively, with a time response of 50 femtoseconds for all gates. In addition, it was found that the calculation of manufacturing tolerance can be considered as a practical method to consider the production error of logic gates. In the end, this paper provides positive outcomes for the future of computational integrated circuits in photonics. [ABSTRACT FROM AUTHOR]

This paper proposes field programmable gate array (FPGA) realization of fuzzy PI controller for typical industrial process called stirred tank heater system. Due to the complex nature of fuzzy controller families, its implementation on digital signal processors (DSPs) result computational time delay which, in other words, makes the processing speed slower. To address the limitations of DSP implementation, an alternative digital hardware programmable device called FPGAs are being largely used for digital implementation of algorithms with higher computational speed and accuracy. The proposed work is inspired by this quality of FPGAs and aims to take advantage of reliable performance of fuzzy PI controllers with its complexity and having no considerable impact on processing speed. Here, fast and novel design approach for rapid prototyping of fuzzy PI controller for stirred tank heater is presented thoroughly. Xilinx system generator SIMULINK add on from VIVADO is used to generate very high-speed integrated circuit hardware description language (VHDL) directly from MATLAB. The developed controller for stirred tank system is verified in fixed point arithmetic using Xilinx Simulink blocks. The VHDL code is then generated, synthesized, implemented, and made ready for physical implementation on Kintex-7 evaluation board. [ABSTRACT FROM AUTHOR]

This paper presents a democratic nature inspired evolvable chain (shorten as EVONChain), a scalable and decentralized public blockchain architecture with high throughput and fast confirmation. EVONChain decouples the function of a full blockchain node into two processes of consensus that are completed separately in two connected networks, with a small number of high-performance cloud nodes in the inner network responsible for collecting and validating transactions, packaging blocks, as well as implementing a consistent replication, and a huge number of low-performance user nodes, connected through the Mobile Edge Computing (MEC) in the outer network, are responsible for the Proof of Intelligence (PoI) work, a novel Proof of Work (PoW) mechanism that resists Application-Specific Integrated Circuit (ASIC) computing and enables "one-CPU-one-vote". To make full use of inner network bandwidth, the graph-chain consensus protocol with high bandwidth utilization called ORIC was deployed to EVONChain. The relationship between the inner and outer networks is enhanced through the bi-tiered incentive mechanism. We developed an EVONChain simulator and evaluated EVONChain on it with up to 5000 nodes. Under the inner network bandwidth of 1.5Gbps, EVONChian can achieve a throughput of close to 375,000 transactions per second, with a block interval of 10s and an orphaned block rate of less than 7%. Simulation results show that EVONChain can drastically increase the performance scalability of practical high-frequency applications, and greatly decrease the confirmation time to a minute level. [ABSTRACT FROM AUTHOR]

This paper proposes a new design for a π-phase shifter and two π/2-phase shifters, which are based on a two-dimensional rods-in-air photonic crystal waveguide. The proposed devices have been designed using both triangular and square lattice photonic crystal structures. Notably, these phase shifters do not require any external energy source to operate. To calculate the band diagram of the PhC, the plane wave expansion method was utilized, while finite-difference time-domain simulation methodology was used to estimate and examine the performance of the proposed phase shifters. The simulation results demonstrate that the proposed π-phase shifter can achieve a bandwidth of 1.5THz, whereas the π/2-phase shifters, designed on triangular and square lattice can achieve bandwidths of 1.9THz and 1.35THz, respectively. Due to their straightforward design structure and energy independence, these devices are well-suited for future generations of all-optical photonic integrated circuits. [ABSTRACT FROM AUTHOR]

In this paper, we developed and investigated superconducting integrated circuits designed to match the impedances of a generator represented by a flux-flow oscillator based on a long Josephson junction and a detector based on a superconductor–insulator–superconductor tunnel junction in the subterahertz frequency range. The structures were modeled using the transfer matrix method. Designs were also calculated in the program of numerical three-dimensional modeling. A qualitative agreement was found between the results obtained by two methods. Three samples with different topologies were designed, covering the frequency range of 250–680 GHz at a level of –2 dB. [ABSTRACT FROM AUTHOR]

Semiconductors are an important electronic component and play a central role in many industrial fields, whose production system is spread all over the world, involving trade in many raw materials, mechanical equipment, and finished products. Comprehending a broad global production picture of the semiconductor industry can be an arduous task. To tackle this complexity, the social network analysis method was used to capture the flows of products between economies in the semiconductor industrial chain. This study analyzed the evolution of the trade pattern of four key commodities in the semiconductor industrial chain, with a focus on identifying the status of major economies in the global semiconductor trade system. Additionally, the influencing factors of the formation of the trade networks were explored by using the Exponential Random Graph Model. The results showed that: (1) From 2001 to 2019, the import and export trade pattern of four key commodities in the semiconductor industrial chain has shown the characteristics of "rising in the east and decreasing in the west", but the change range shows strong commodity heterogeneity, the change of the spatial pattern of integrated circuits trade is the most significant, and the integrated circuits trade proportion of Asian economies has increased hugely with more than 80%. (2) The trade connectivity of various commodities in the semiconductor industrial chain has increased, upstream support products with high technical requirements such as wafers and equipment have the lowest average degree and weak trade liquidity, and the average degree of trade network of packaging materials and integrated circuits is relatively high, with strong trade liquidity and closer and more prosperous trade connections. (3) From 2001 to 2019, the "core-periphery" system of global semiconductor industry trade has changed significantly, with the core circle undergoing obvious iterative reorganization. for example, China and Singapore have achieved status improvement to the core circle in the base materials trade network, while Malaysia has been squeezed into the semi-peripheral circle. (4) The formation of trade networks of various commodities in the semiconductor industrial chain was driven by three aspects: network self-organization, exogenous endowment attribute, and exogenous network embeddedness. Among them, the influence of the technological innovation level of economies on different commodity trade networks showed heterogeneous. [ABSTRACT FROM AUTHOR]

Topological domain structures have drawn great attention as they have potential applications in future electronic devices. As an important concept linking the quantum and classical magnetism, a magnetic Bloch point, predicted in 1960s but not observed directly so far, is a singular point around which magnetization vectors orient to nearly all directions. Here we show polar Bloch points in tensile-strained ultrathin ferroelectric PbTiO3 films, which are alternatively visualized by phase-field simulations and aberration-corrected scanning transmission electron microscopic imaging. The phase-field simulations indicate local steady-state negative capacitance around the Bloch points. The observation of polar Bloch points and their emergent properties consequently implies novel applications in future integrated circuits and low power electronic devices. Authors predict polar Bloch points with negative capacitance in tensile-strained ultrathin ferroelectric PbTiO3 film by phase-field simulations, observing their polarization structures by scanning transmission electron microscopic imaging. [ABSTRACT FROM AUTHOR]

In implantable electrophysiological recording systems, the headstage typically comprises neural probes that interface with brain tissue and integrated circuit chips for signal processing. While advancements in MEMS and CMOS technology have significantly improved these components, their interconnection still relies on conventional printed circuit boards and sophisticated adapters. This conventional approach adds considerable weight and volume to the package, especially for high channel count systems. To address this issue, we developed a through-polymer via (TPV) method inspired by the through-silicon via (TSV) technique in advanced three-dimensional packaging. This innovation enables the vertical integration of flexible probes, amplifier chips, and PCBs, realizing a flexible, lightweight, and integrated device (FLID). The total weight of the FLIDis only 25% that of its conventional counterparts relying on adapters, which significantly increased the activity levels of animals wearing the FLIDs to nearly match the levels of control animals without implants. Furthermore, by incorporating a platinum-iridium alloy as the top layer material for electrical contact, the FLID realizes exceptional electrical performance, enabling in vivo measurements of both local field potentials and individual neuron action potentials. These findings showcase the potential of FLIDs in scaling up implantable neural recording systems and mark a significant advancement in the field of neurotechnology. [ABSTRACT FROM AUTHOR]

Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we propose the design of a track and hold (T&H) integrated circuit that is able to sample an incoming high-speed PAM4 signal and feed it to an analog to digital converter (ADC). This building block acts as a front-end in optical transceivers carrying sensitive data, where power consumption and cost are a primary concern. The proposed architecture is discussed in detail and a design approach based on the switched capacitor architecture is examined and simulated. Parasitic based capacitance is utilized to hold the signal, and post-layout simulation shows a low power consumption of 42 mW while sampling a 1 GS/s PAM4 signal at 200 MSps (Mega-samples per second). Our circuit has a 10 times lower power consumption compared to a similar implementation in BiCMOS and a comparable power consumption to similar CMOS implementations but with a higher output voltage swing and far less smaller area. Our circuit is designed for PAM4 signals but can be used for NRZ as well, which is a first of its kind in sample and hold circuits targeting serial modulated signals such as PAM4. [ABSTRACT FROM AUTHOR]

This paper presents design and numerical investigations of an ultra-compact, and highly-efficient plasmonic absorber based on metal–insulator–metal waveguides. The proposed device offers multiple narrow-band absorption at visible and near-infrared wavelengths with peak absorbance between 81 and 100%. The finite element method has been used to simulate the proposed structure. The simulation results show that the resonance wavelengths can be easily modulated by tuning the coupling distances between the input and output ports and the triangular resonators. To find the optimized size of the proposed structure, maximize its efficiency, and attain narrow-band resonances, a parameterized genetic algorithm has been used. Taking into account the obtained notable specifications of the proposed structure, it can contribute to the development of miniaturized and efficient optical components for photonic integrated circuits. [ABSTRACT FROM AUTHOR]

Reduction of the crosstalk (CT) between contiguous photonic components is still a big challenge in fabricating high packing density photonic integrated circuits (PICs). Few techniques to accomplish that goal have been offered in recent years but all in the near-IR region. In this paper, we report a design for realizing a highly efficient CT reduction in the MIR regime, for the first time to the best of our knowledge. The reported structure is based on the silicon-on-calcium-fluoride (SOCF) platform with uniform Ge/Si strip arrays. Using Ge strips shows better CT reduction and longer coupling length (Lc) than the conventional Si based devices over a wide bandwidth in the MIR region. The effect of adding a different number of Ge and Si strips with different dimensions between two adjacent Si waveguides on the Lc and hence on the CT is analyzed using both full vectorial finite element method and 3D finite difference time domain method. An increase in the Lc by 4 orders of magnitude and 6.5 times are obtained using Ge and Si strips, respectively, compared to strips-free Si waveguides. Consequently, crosstalk suppression of − 35 dB and − 10 dB for the Ge and Si strips, respectively, is shown. The proposed structure is beneficial for high packing density nanophotonic devices in the MIR regime, such as switches, modulators, splitters, and wavelength division (de)multiplexers, which are important for MIR communication integrated circuits, spectrometers, and sensors. [ABSTRACT FROM AUTHOR]

Knowledge of the positions, polarizations, and local environment effect on the light coupling efficiency from a single photon source to an optical waveguide is critically important for the development of an integrated single photon emitter. In this paper, we contribute to a holistic investigation on the dependence of the wideband coupling efficiency and Purcell enhancement factor on the emitter positions, orientations, refractive indices and geometrical parameters of SiNx waveguides for broadband CMOS-compatible quantum photonic integrated circuits using FDTD analysis in very near-infrared ranges. The obtainable spectral range with respect to SiNx waveguide dimensions and optical parameters, the polarization-dependent coupling efficiency of a single photon source with respect to the displacement from the waveguide edge facet, the horizontal and vertical positional variations, and the etching required to maximize and maintain the coupling efficiency values over the spectral range are discussed. [ABSTRACT FROM AUTHOR]

A study was made of a thermal interface based on a two-dimensional allotropic modification of carbon (graphene), presented in the form of a powder, for cooling integrated circuits. Such physical properties of the thermal interface as thermal conductivity, heat capacity, thermal diffusivity, and density are determined by the empirical method. The process of heat transfer in the most efficient thermal interface sample during the operation of integrated circuits in the ANSYS engineering analysis system is presented. The prospects of using pressed graphene powder as a thermal interface in order to eliminate the use of a binder are described. The paper also makes a comparison with the most effective type of thermal interfaces currently in use. [ABSTRACT FROM AUTHOR]