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We validate a model which is a combination of multiple trapping and release and percolation model for describing the conduction mechanism in amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT). We show that using just multiple trapping and release or percolation model is insufficient to explain TFT behavior as a function of temperature. We also show the intrinsic mobility is dependent on temperature due to scattering by ionic impurities or lattice. In solving the Poisson equation to find the surface potential and back potential as a function of gate voltage, we explicitly allow for the back surface to be floating, as is the case for a-IGZO transistors. The parameters for gap states, percolation barriers and intrinsic mobility at room temperature that we extract with this comprehensive model are in good agreement with those extracted in literature with partially-complete models. [ABSTRACT FROM AUTHOR]

We report on the impact of source/drain (S/D) metal (molybdenum) etch and the final passivation (SiO2) layer on the bias-stress stability of back-channel-etch (BCE) configuration based amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). It is observed that the BCE configurations TFTs suffer poor bias-stability in comparison to etch-stop-layer (ESL) TFTs. By analysis with transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS), as well as by a comparative analysis of contacts formed by other metals, we infer that this poor bias-stability for BCE transistors having Mo S/D contacts is associated with contamination of the back channel interface, which occurs by Mo-containing deposits on the back channel during the final plasma process of the physical vapor deposited SiO2 passivation. [ABSTRACT FROM AUTHOR]