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Drain-extended MOSFET (DEMOS) with halo implant induced laterally asymmetric channel doping shows anomalous characteristics across bias and temperature that cannot be captured by existing models. The transconductance (gm) maxima in the linear region is found to be not only a function of the peak mobility but also the halo doping density. In the saturation region, the gm characteristics show a nonmonotonic “hump” induced by the halo-region/channel-region junction barrier. Another key care-about for analog design - the drain current (ID) mismatch, also exhibits unique characteristics with excess mismatch in the weak-inversion (WI) region, in particular at low temperature. In addition, the anomalous flicker noise (1/ƒ noise) trends in the presence of high-trap density in the halo region of halo-implanted DEMOS are also discussed. In this work, we propose an analytical model based on the equivalent conductance and impedance field theory to capture these effects. The proposed model is in good agreement with measurements and numerical device simulations using technology computer-aided design (TCAD) of DEMOS across a different oxide thickness, geometry, bias, and temperature. [ABSTRACT FROM AUTHOR]

In this brief, we present an improved model of bulk charge effect for both drain current (${I}_{\text {DS}}$) and capacitances and its implementation in the industry standard Berkeley short-channel IGFET model (BSIM)-BULK model. The proposed model captures all the well-known and important bulk charge effects, as the Abulk term does for BSIM3/BSIM4. The model is validated with the experimental and technology computer-aided design (TCAD) data. The proposed model enhances the fitting accuracy for ${I}_{\text {DS}}$ , and more importantly its derivatives and capacitances too. [ABSTRACT FROM AUTHOR]

We present an analytical modeling approach for drain current (${I}_{D}$) mismatch in lateral nonuniformly doped (NUD) MOSFETs. The model uses the carrier number fluctuation theory to include the effect of random dopant fluctuations (RDFs) on inversion charge fluctuation (ICF) in different operating regions. Our analysis shows that the conventional models for uniformly doped device underestimate the ${I}_{D}$ mismatch by one-to-two orders of magnitude at low gate voltages in NUD devices. We have also considered the effect of RDF on mobility fluctuation (MF), which shows its significant role in strong inversion (SI). To investigate the physical mechanism leading to such a behavior, extensive technology computer-aided design simulations are performed for various conditions of bias, doping profiles, and temperature. Using the impedance field method to calculate the relative contributions of RDF to ICF and MF, we show that our model can successfully capture the drain current mismatch across subthreshold to SI in the NUD device. [ABSTRACT FROM AUTHOR]

We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model. [ABSTRACT FROM AUTHOR]

We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source–drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage ( V\mathrm{ DS}) , gate-to-source voltage ( V\mathrm{ GS}) , gate length ( LG) , substrate doping concentration ( N\mathrm{ sub}) , and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data. [ABSTRACT FROM AUTHOR]

This paper presents a fast and accurate way to design and optimize LC oscillators using the inversion coefficient ( IC). This methodology consists of four steps: linear analysis, nonlinear analysis, phase noise analysis, and optimization using a figure of merit. For given amplitude of oscillation and frequency, we are able to determine all the design variables in order to get the best trade-off between current consumption and phase noise. This methodology is demonstrated through the design of Pierce and cross-coupled oscillators and has been verified with BSIM6 metal oxide semiconductor field effect transistor compact model using the parameters of a commercial advanced 40 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current $ I_{{\text {edge}}}$ at the shallow trench isolation edge. Accurate, efficient, and scalable model for $ I_{{\text {edge}}}$ is developed by finding the key differences between $ I_{{\text {edge}}}$ and main device drain current ( $ I_{{\text {main}}}$ ). It is found that $ I_{{\text {edge}}}$ has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to $ I_{{\text {main}}}$ . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage. [ABSTRACT FROM PUBLISHER]

The downscaling of CMOS processes has led to devices with an impressive RF performance. Advanced nanoscale RF MOSFETs present very high transit frequency, which can be traded off with lower power consumption, by shifting the operating point towards the weak inversion (WI) regime. This paper explores whether the simple RF schematics and models used in strong inversion remain valid in moderate or even down to deep WI regions for nanoscale devices. A simple RF equivalent circuit is proposed, leading to first-order analytical expressions, which are able to describe the RF small-signal behavior of nanoscale MOSFET, including noise, across all inversion levels. Using these expressions it is possible to extract the values of all the RF components and noise model parameters directly from measurements. The analytical models are compared to RF measurements of a commercial state-of-the-art 40-nm CMOS process and to the advanced BSIM6 compact bulk MOSFET model, showing very good accuracy. [ABSTRACT FROM PUBLISHER]

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source–drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node. [ABSTRACT FROM PUBLISHER]