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In-memory computing (IMC), leveraging emerging memories, holds significant promise in overcoming memory limitations and improving energy efficiency. However, the prevailing IMC array structure based on serially connected transistors and memory cells (1T1R/2T2R), along with the signed weight mapping scheme, can lead to asymmetrical weight sensing issues (AWS) due to electrical asymmetry within the 1T1R/2T2R structure, particularly in highly scaled cells where the transistor’s resistance becomes significant. In this paper, we propose and fabricate an electrically symmetric memory cell based on a physically isolated 2T2R structure for IMC. This design aims to enhance the precision and density of RRAM-based IMC arrays. The 2T2R cells are manufactured using the back-end-of-line (BEOL) process of a commercial 40 nm technology platform. The feasibility of this design is verified through measured and simulated results, showcasing its capability to address the issue of AWS. Compared to conventional 2T2R cells, this design achieves a considerably smaller transistor footprint without compromising accuracy, while also improving integration density by 42.2%. These innovative memory cell advancements have the potential to further advance high-energy-efficient IMC technology. [ABSTRACT FROM AUTHOR]

Mott devices, featuring low hardware cost and high energy efficiency, have been demonstrated as a key oscillatory element in artificial neurons to enable spiking neural networks (SNNs) such as conversion-based SNNs (CSNNs). However, there will be inevitably non-ideal fluctuation in the oscillation behavior, causing the accuracy degradation of networks. In this paper, we investigate the Mott neuronal oscillation fluctuation (NOF) through experiments and modeling. The results show that the NOF phenomenon conforms to Gaussian distribution and originates from thermal fluctuation induced switching voltage variations. We construct a two-layer CSNN for image recognition tasks to study the NOF effect and propose the activation function boundary (AFB) method to strengthen the stability of the network. The results indicate that AFB can improve the accuracy of CSNN by up to 15.5% by tightening output distribution. [ABSTRACT FROM AUTHOR]

In this work, thermal stability of InZnO (IZO) and Al‐doped InZnO (IAZO) transistors are studied. With a consecutive annealing pre‐treatment at 300 ℃ in air, the IAZO transistors show superior electrical properties to the IZO transistors, demonstrating that element Al plays a role as stabilizer for maintaining device performance. Our work paves the way for practical application of the oxide transistors in back‐end‐of‐line (BEOL) scenarios. [ABSTRACT FROM AUTHOR]

Processing-in-memory (PIM) architecture has been proposed to accelerate state-of-the-art neuro-inspired algorithms, such as deep neural networks. In this article, we present PIMulator-NN, an event-driven, cross-level simulation framework for PIM-based neural network accelerators. By employing an event-driven simulation mechanism, PIMulator-NN is able to model architecture details and capture design details of the architecture. Moreover, we integrate the main-stream circuit-level simulation framework with PIMulator-NN to accurately simulate the area, latency, and energy consumption of analog computation units. To demonstrate the usage of PIMulator-NN, we implement several PIM designs with PIMulator-NN and perform detailed simulation. The simulation results show that memory access and interconnects make considerable impacts on system-level performance and energy. Note that such results are hard to be captured by conventional performance model-based estimations. We found some anti common-sense results while modeling the architecture details with PIMulator-NN. With several architecture templates, PIMulator-NN provides the users with a platform to build up their PIM architecture quickly. PIMulator-NN is able to capture the impacts of different design choices (e.g., dataflow, interconnect, data parallelism, etc.), and this could enable users to explore their design space efficiently. [ABSTRACT FROM AUTHOR]

Neuromorphic engineering offers a promising route toward intelligent and low power computing systems that may find applications in artificial intelligence and the Internet. Construction of neuromorphic systems, however, requires scalable nanodevices that could implement the key functionalities of biological synapses. Here, we demonstrate an artificial synaptic device consisting of a Ti/yttria-stabilized-zirconia (ZrO2:Y)/Pt memristive structure, where the loss microstructure, high oxygen vacancy concentration, and resultant high ionic conductivity in ZrO2:Y facilitate the oxygen vacancy migration and filament evolution in the devices, leading to a bipolar artificial synapse with low forming and operation voltages. As the thickness of ZrO2:Y film increases, a transition from bipolar to unipolar resistive switching was observed, which can be ascribed to the competing vertical and radial ion transport dynamics. The emergence of unipolar switching has in turn allowed the device to exhibit metaplasticity, a history dependent plasticity that is important for memory and learning functions. This work thus demonstrates on-demand manipulation of ionic transport properties for building synaptic elements with rich functionalities. [ABSTRACT FROM AUTHOR]

Artificial neurons are the fundamental elements in neuromorphic computing systems. Studies have revealed neuronal spike‐rate adaptation owing to intrinsic plasticity that neurons will adapt to the spiking patterns and store the events in the background spiking through clustered neuronal spiking. The event can be reactivated by specific retrieval clues instead of solely relying on synaptic plasticity. However, the neural adaptation, as well as the interactive adaptations of neuronal activity for information processing, have not been implemented. Herein, an artificial adaptive neuron via in materia modulation of the VO2/HfO2 based dual‐mode memristor is demonstrated. By changing the conductance of the HfO2 layer, the firing threshold can be modulated, thus the excitability and inhibition can be adjusted according to the previous stimuli without any complex peripherals, showing an adaptive firing rate even under the same stimuli. The artificial neuron clusters can emulate the concept of neuronal memory and neural adaptation, demonstrating spatiotemporal encoding capabilities via the correlated neural firing patterns. This conceptual work provides an alternative way to expand the computation power of spiking neural networks by exploiting the neural adaptation and could be enlightenment to maximize the synergy across both synapse and neuron in neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

Pulse-to-pulse variability (PPV) is a vital nonideal effect in analog resistive memory, particularly for online training in emerging computing paradigms. The reported PPVs usually show two seemingly contradictory properties: large PPV amplitude between neighboring write pulses but statistically stable switching curves. In this article, a new insight is proposed to unambiguously decouple PPV into two independent components: variability and curve fluctuation. Furthermore, a phenomenological modeling and parameter extraction method is proposed to capture this characteristic. The proposed model can facilitate the exploration of PPV impact on neural network accuracy for online training. [ABSTRACT FROM AUTHOR]

With the rapid growth of computer science and big data, the traditional von Neumann architecture suffers the aggravating data communication costs due to the separated structure of the processing units and memories. Memristive in-memory computing paradigm is considered as a prominent candidate to address these issues, and plentiful applications have been demonstrated and verified. These applications can be broadly categorized into two major types: soft computing that can tolerant uncertain and imprecise results, and hard computing that emphasizes explicit and precise numerical results for each task, leading to different requirements on the computational accuracies and the corresponding hardware solutions. In this review, we conduct a thorough survey of the recent advances of memristive in-memory computing applications, both on the soft computing type that focuses on artificial neural networks and other machine learning algorithms, and the hard computing type that includes scientific computing and digital image processing. At the end of the review, we discuss the remaining challenges and future opportunities of memristive in-memory computing in the incoming Artificial Intelligence of Things era. [ABSTRACT FROM AUTHOR]

The von Neumann bottleneck and memory wall have posed fundamental limitations in latency and energy consumption of modern computers based on von Neumann architecture. In-memory computing represents a radical shift in the computer architecture that can address such problems by merging computing functions within the memory itself. In this article, we review the emerging nonvolatile memory devices, such as resistance-based and charge-based memory devices, that are explored for in-memory computing applications. We will provide an overview of the materials, mechanisms, and integration of these devices, and discuss the optimizations at the device and array levels that are required to better support in-memory computing. Recent progress in the application of in-memory computing in artificial neural networks, spiking neural networks, digital logic in memory as well as hardware security will also be discussed. Finally, we will discuss the remaining challenges in this field and potential pathways to address them. [ABSTRACT FROM AUTHOR]

Recent studies indicate that synaptic scaling is a vital mechanism to solve instability risks brought by the positive feedback of synaptic weight change related with standalone Hebbian plasticity. There are two kinds of synaptic scaling in the neural network, including local scaling and global scaling, both important for stabilizing the neural function. In this paper, for the first time, local synaptic scaling is emulated based on the MoS2 neuristor. The first‐principle calculation reveals that synaptic scaling achieved by the neuristor is associated with an internal residual Li+‐related weak dynamical process. Experimental results show the potential of achieving global synaptic scaling by the same device. Moreover, inspired by the synaptic scaling in the human brain, a new method of weight mapping called weight scaling mapping (WSM) is proposed to improve the stability of an artificial neural network (ANN). The simulation results indicate that WSM can improve the accuracy and anti‐noise ability of the network compared with the traditional mapping method. These findings provide new insight into bionic research and help advance the construction of stable neuromorphic systems. [ABSTRACT FROM AUTHOR]

3D integration of vertical resistive random access memory (VRRAM) with organic materials is promising for ultra‐high density flexible data storage. However, it is extremely challenging to heterogeneously fabricate an organic 3D VRRAM due to complicated issues such as chemical/thermal robustness, compatibility of organic/inorganic materials, and processes of stacking/patterning multi‐layer organic/metal films. Herein, an organic flexible 3D VRRAM based on parylene‐C is experimentally demonstrated on a standard complementary metal oxide semiconductor platform for the first time. The proposed 3D VRRAM can be homogenously fabricated based solely on parylene‐C (except the metal electrodes), significantly facilitating the 3D integration owing to chemical stability and compatibility with standard photolithography patterning. The flexible 3D organic memory arrays demonstrate great memory characteristics including retention time >105 s, endurance cycles >300, and resistance ON/OFF ratio >10. Further, a finite element analysis is established to model and investigate the scaling potential of the organic 3D VRRAM. The simulation results indicate the elevated temperature during programming could be catastrophic for ultra‐high density 3D VRRAM if the feature size approaches ≈100 nm or below, urging the containment of programming power to avoid thermal issues as well as to save energy consumption. [ABSTRACT FROM AUTHOR]

Compressed sensing with a tunable random sampling strategy has great potential in reducing the energy/time consumption during the constant acquisition of external information, thereby it is considered one of the most promising sensing strategies in edge-terminal. In this letter, a novel tunable stochastic oscillator (TSO) based on the VO2/TaOx structure was proposed and employed as the core controlling device for compressed sensing. The TSO is jointly governed by the metal-insulator-transition (IMT) based threshold switching of the VO2 layer and the stochastic resistive switching by the TaOx layer. The tunable memristor/resistor in series can modulate the oscillation frequency of the TSO. The orthogonal matching pursuit (OMP) algorithm is implemented to reconstruct the compressed sparse signals, demonstrating a good performance of TSO in compressed sensing. [ABSTRACT FROM AUTHOR]

Beyond the great success in machine learning (ML), the engineering community has been actively exploring neuromorphic computing systems based on spiking neural networks (SNNs). In the preliminary SNN, the neuronal information is simply encoded by the firing rate, which limits the volume of information in a certain spike pattern. Studies of the biological nervous system have discovered neuronal cooperativity, where flow of neural information is collaboratively encoded and carried by the spatiotemporal stamp and the correlated neuronal activity. In this study, by encoding the control pattern on the dual gates, a MoS2‐based neuristor is exploited to program spatiotemporal information and neuronal correlations via the device's internal dynamics as well as the network topology, and a spiking correlated neural network (SCNN) is demonstrated. This correlated neural network not only succeeds in identifying the patterns with translational and rotational symmetry but also correctly reveals the rotated angles. Compared with conventional SNNs, the dimension of information flow in SCNNs can be greatly enlarged by taking advantage of the synergy between the rate coding and the neuronal correlations. This proof‐of‐concept work provides the potential to achieve high‐volume information processing with the simplified circuitry of neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

In a digital–analog mixed neuromorphic system, various complex peripheral circuits may offset the integration and energy efficiency advantages of the dense crossbar. To simplify the peripheral circuits, a self-activation neural network (SANN) is proposed based on a passive crossbar array formed by the rectified memristive (ReMem) cell. The ReMem cell is a dual-mode resistive switching device with a VO2/TaOx bilayer structure. It shows a hybrid switching behavior including volatile threshold switching and multilevel nonvolatile resistive switching. This unique feature enables not only simultaneously self-selection and distributed activation, but also weight storage. The concept of SANN is theoretically examined, and a neural network is constructed and trained with SANN based on the proposed devices to perform recognition on handwritten digits in the MNIST database. Compared with neuromorphic computing systems using the CMOS-based activation module and additional selective element, the results show comparable recognition accuracy with reduced circuitry complexity. The proposed SANN can be a promising alternative to realize neural network computing systems with simplified peripheral circuits. [ABSTRACT FROM AUTHOR]

For resistive RAM (RRAM)-based deep neural network (DNN), random telegraph noise (RTN) causes accuracy loss during inference. In this article, we systematically investigated the impact of RTN on the complex DNNs with different data sets. By using eight mainstream DNNs and four data sets, we explored the origin that caused the RTN-induced accuracy loss. Based on the understanding, for the first time, we proposed a new method to estimate the accuracy loss. The method was verified with other ten DNN/data set combinations that were not used for establishing the method. Finally, we discussed its potential adoption for the cooptimization of the DNN architecture and the RRAM technology, paving ways to RTN-induced accuracy loss mitigation for future neuromorphic hardware systems. [ABSTRACT FROM AUTHOR]

In this letter, we experimentally demonstrated a novel resistive device with a hybrid switching mode that can be alternated between volatile threshold switching and non-volatile resistive switching. The device consists of dual-functional layers VO2 /HfO2 sandwiched by symmetrical TiN electrodes. A >20 unified ratio for selectivity and memory window is obtained. Owing to the stable resistive behavior of HfO2 and insulator-metal transition of VO2, the device shows excellent uniform switching parameters in both switching modes with a high on-state current density (1E4 A/cm2) and fast switching/recovery speed (< 30 ns). This self-selective resistive memory is of great potential in the high-density crossbar array, particularly for the future 3D-Vertical resistive random access memory (RRAM) integration. [ABSTRACT FROM AUTHOR]

In this letter, a new reliability phenomenon, named early-stage resistance fluctuation (ERF), in analog resistive random-access memory (RRAM) devices and its impact on the neuromorphic computing are investigated. ERF is found to be a non-negligible random fluctuation behavior of RRAM resistance within ~10,000s after verification due to stochastic migration of vacancies. As a result, ERF can induce weight noise in RRAM-based neural network even with write-verify operation and cause a significant (~42%) drop of recognition accuracy on the MNIST dataset recognition tasks. An approach incorporating automatic early-stop and dropout during training is proposed to reduce the impacts of ERF. Results show that the recognition accuracy with ERF can be improved from 58% to 96% after adopting the proposed optimization method. [ABSTRACT FROM AUTHOR]

Memory cells have always been an important element of information technology. With emerging technologies like big data and cloud computing, the scale and complexity of data storage has reached an unprecedented peak with a much higher requirement for memory technology. As is well known, better data storage is mostly achieved by miniaturization. However, as the size of the memory device is reduced, a series of problems, such as drain gate‐induced leakage, greatly hinder the performance of memory units. To meet the increasing demands of information technology, novel and high‐performance memory is urgently needed. Fortunately, emerging memory technologies are expected to improve memory performance and drive the information revolution. This review will focus on the progress of several emerging memory technologies, including two‐dimensional material‐based memories, resistance random access memory (RRAM), magnetic random access memory (MRAM), and phase‐change random access memory (PCRAM). Advantages, mechanisms, and applications of these diverse memory technologies will be discussed in this review. [ABSTRACT FROM AUTHOR]

We propose an electronic synapse based on an Al: HfO2 metal–ferroelectric–metal (MFM) capacitor with multi-level characteristics. The device demonstrates excellent multilevel behavior, linearity, weight update symmetry, and low static power consumption. Furthermore, an artificial neural network (ANN) based on this capacitor is built and evaluated through SPICE and MATLAB simulations. The performance indicates that more than 78% accuracy and nJ/ms dynamic speed–energy efficiency in recognizing the standard MNIST handwritten digits are achieved, showing the capability of high-density integration and low energy consumption of the capacitive ANNs. [ABSTRACT FROM AUTHOR]

Hamming code is a linear error-correcting code widely used in memory and telecommunication. For the first time, here we put forth an approach to analyzing Hamming codes in hardware using networks consisting of memristors. Such networks are capable of detecting and correcting potential bit errors in Hamming codes in a high-speed and energy-efficient way, where the parity-check matrix is stored in the memristor crossbar array and the syndrome vector is represented by the states of the output unipolar memristors whose resistance flipping naturally implements vector-matrix multiplication with modulo 2. Our experimental results demonstrate that the output syndrome vector is able to correctly represent the position of the bit error whenever it exists, and subsequent correction can thus be applied by flipping the bit identified. The energy consumption using the present network has decreased by >100 times compared with GPU while >1000 times compared with CPU. [ABSTRACT FROM AUTHOR]

Memristive devices based on electrochemical processes are promising candidates for next-generation memory and neuromorphic applications. The redox processes happening at the interfaces are crucial steps for the ionization as well as generation of counter charges, and are thus indispensable for successful resistive switching, but their detailed mechanism has not been fully clarified. Here, we study the interfacial redox reactions in the forming process of memristive devices based on valence change and electrochemical metallization, using high-resolution electron microscopy and electrostatic force microscopy observations. We show direct evidence for the anodic oxidation of oxygen ions and cathodic reduction of moisture in HfO2- and Ta2O5-based valence change cells, which could take place in different horizontal locations. We further found that the anodic reactions always led to more pronounced structural damage to the electrode, indicating the possibility of additional cathodic reactions without producing gaseous products. When an active electrode is present, oxidation of metal atoms takes place at the anodic interface instead. Further investigations on electrochemical metallization cells have identified Cu ionization and moisture reduction as the anodic and cathodic reactions, respectively, and formation of Cu nuclei at the cathodic interface was directly observed. These findings with microscopic evidence could facilitate future development of memristive devices. [ABSTRACT FROM AUTHOR]

In this letter, the impacts introduced by oxygen-scavenging metal (Ti), including forming voltages variation and resistances dispersion in high/low states of HfOx-based RRAM devices, were investigated. Based on experiments, it is concluded that Ti atoms during physical vapor deposition process can randomly penetrate into the bulk of HfOx and are intended to randomly create the initial oxygen vacancies, thus causing the performance degradation. Moreover, a novel structure with an atomic layer deposition-TiN buffer layer inserted between oxygen-scavenging Ti and HfOx layers was proposed and experimentally demonstrated to reduce the impacts of Ti penetration, which further improves vacancy-creating approach. It was experimentally verified that with the help of incorporating a TiN buffer layer, the uniformity of switching parameters, such as forming voltage and resistance, was effectively improved. The understanding and improvement of device variation caused by oxygen-scavenging metal in oxides-based resistive random access memory (RRAM) are useful for further development of highly reliable RRAM technology. [ABSTRACT FROM PUBLISHER]

The development of smart, scalable, and power efficient computers relies on innovative technologies that can distribute memory alongside processing, such as emerging neuromorphic computing and in-memory logic technologies. Here, a type of vertical 3-terminal oxide based nanoionic device capable of implementing heterosynaptic plasticity and nonvolatile Boolean logic simultaneously is demonstrated. The heterosynaptic plasticity endows the devices with facilely tunable synaptic kinetics via tailoring modulatory signals, which is shown to be crucial for achieving optimized learning scheme, therefore offering promising building blocks for neuromorphic computing. Furthermore, it is demonstrated that these heterosynaptic devices can simultaneously be utilized to implement nonvolatile Boolean logic with improved efficiency compared with existing approaches, therefore implying in-memory computing potentialities. The heterosynaptic devices with such multifunctionality thus hold great potential for next-generation non-von Neumann computing applications. [ABSTRACT FROM AUTHOR]

Impact of heavy-ion irradiation on the TaOx-based resistive random-access memory (RRAM) is investigated in this work. After Br ion irradiation, the set voltage of TaOx-based RRAM shows slight change, and negative shift of the forming voltage is observed. For the resistance change of TaOx-based RRAM devices induced by irradiation, the resistance of the low resistance state (LRS) illustrates acceptable change, while the resistance of the high resistance state (HRS) is quite sensitive to heavy ion irradation. Some irradiated devices even change from the HRS into the LRS, which results in disappeared memory window and may be attributed to the displacement damage in the dielectric layer. These results indicate that TaOx-based RRAM devices need to be carefully designed for future space applications. [ABSTRACT FROM PUBLISHER]

Crossbar array architecture is usually used for the high-density integration of the RRAM device. However, the large sneak current in the passive crossbar array limits the increase in the integration density. In this brief, the bipolar \TiN/TaOx/\Pt RRAM device is proposed as the dynamic selector for the unipolar \Pt/TaOx/\Pt RRAM device to suppress the sneak current in the crossbar array. The testing results show that the bipolar RRAM can act as a good selector, and the sneak current is reduced by about two orders estimated by the 1/2 Vread voltage scheme. With the suppressed sneak current, the maximum size of the crossbar array with the bipolar RRAM selector can be increased to more than 1 Mb according to the simulation results, indicating that the bipolar RRAM selector has great potential for the high-density memory applications. [ABSTRACT FROM AUTHOR]

In this brief, the total ionizing dose (TID) effects of \gamma rays generated from a ^60\Co source on the \TaOx-based resistive switching memory (resistive random-access memory, RRAM) is investigated. The low-resistance state (LRS) of the RRAM is immune to TID effects, whereas the sensitivity of the high-resistance state (HRS) of RRAM to TID effects depends on the dimensions of the device, including the thickness of the oxide film and the area of the device. The HRS of the device with large area and thick oxide layer is vulnerable to TID effects and has a high probability to change into the LRS. Further investigation found that the lower the high resistance, the higher the failure rate of the RRAM device under TID impact, which indicates that the multilevel cell of RRAM should be carefully designed for space system applications considering the radiation effects. The failure of the HRS under TID is explained by defect generation in the oxide film. [ABSTRACT FROM PUBLISHER]

This paper discusses the resistive switching devices based on highly compatible silicon-rich-oxide, including silicon monoxide (SiO) and SiON material, which can be fabricated by low temperature process, and thus fully compatible with the back-end CMOS technology. The demonstrated SiO based RRAM suitable for 3D stackable applications shows repeatable unipolar resistive switching behavior with excellent on/off resistance ratio and good retention performance, but a little bit high switching voltage. The presented silicon-rich silicon-oxynitride RRAM device can effectively reduce the switching voltages (∼1 V) and shows good retention capability under 180°C baking as well as fast speed, giving great potentials for 3D stackable and embedded applications. The switching mechanisms in the studied devices are discussed. The method of switching voltage reduction through nitrogen doping, as a kind of defect engineering, can provide some guidelines for RRAM design. [ABSTRACT FROM AUTHOR]

The flash memory technology meets physical and technical obstacles in further scaling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density and low power memory applications based on the vertical channel double gate structure. The proposed VD-NROM with dual-nitride-trapping-layer and vertical structure can achieve four-bit-per-cell storage capability. And the proposed VSAS-FG cell benefits the high programming efficiency, low power and high density capability, which can be realized without any additional mask and can achieve the self-alignment of the split-gate channel and the floating-gate. The two novel flash cell structures can be considered as potential candidates for different flash memory applications. [ABSTRACT FROM AUTHOR]

Resistive random-access memory (RRAM) with the ability to store and process information has been considered to be one of the most promising emerging devices to emulate synaptic behavior and accelerate the computation of intelligent algorithms. However, variation and limited resistance levels impede RRAM as a synapse for weight storage in neural network mapping. In this work, we investigate a TaOx-based RRAM with Al ion local doping. Compared with a device without doping, the device with locally doped Al ion exhibits excellent uniformity and analog characteristics. The operating voltage and resistance states show tighter distributions. Over 150 adjustable resistance states can be achieved through tuning compliance current (CC) and reset stop voltage. Moreover, incremental resistance switching is available under optimized identical pulses. The improved uniformity and analog characteristics can be attributed to the collective effects of reduced oxygen vacancy (Vo) formation energy and weak conductive filaments induced by the local Al ion dopants. [ABSTRACT FROM AUTHOR]