Search

The scaling of microelectronic technologies brings new challenges to the design of complex SoCs. For example, fully synchronous SoCs may soon become unfeasible to build. Asynchronous design techniques increasingly mingle within SoC design procedures to achieve functional and efficient systems, where synchronous modules are independently designed and verified. This is followed by module integration by means of asynchronous interfaces and communication architectures, forming a globally asynchronous, locally synchronous (GALS) system. Among multiple asynchronous design styles, the quasi delay insensitive (QDI) stands out for its robustness to delay variations. When coupled to delay insensitive (DI) codes like m-of-n and to four-phase handshake protocols, the QDI style produces the dominant asynchronous template currently in use. This work presents a technique to reduce the static power consumption of asynchronous QDI circuits using any m-of-n code and a four-phase handshake protocol, by proposing the utilization of a non-classical spacer encoding, namely all-1s. The article shows that the use of the traditional all-0s spacers may lead to static power consumption figures that are in some cases more than twice larger than the static power consumed by all-1s spacers in C-elements, the most common device used in asynchronous templates. Experiments demonstrate the new spacer reduces static power consumption without increase in complexity. [ABSTRACT FROM PUBLISHER]

Implementing on-chip multiprocessors is enabled by the use of deep submicron technologies and constitutes today a daunting task, due to the complexity of their design and verification. The development of such devices can be facilitated by the use of a carefully crafted set of models for each implementation step. This paper proposes the use of such a set of abstract models at several levels. These improve simulation speed and observability in one sense and level of detail and precision in the opposite sense. Initial development tasks such as software development and functionality specification refinement can evolve fast with very abstract models, while confidence in the final implementation can be achieved with lower level models. Our basic multi-processor system on a chip is configurable in several parameters, including number of processors, type of employed communication architecture and combination of abstraction levels used in the description of the distinct modules that compose the model. [ABSTRACT FROM PUBLISHER]

Asynchronous design techniques are gaining attention in the scientific community for their ability to cope with current technologies' problems that the synchronous paradigm may fail to cope with. In fact, fully synchronous SoCs may soon become unfeasible to build. Among multiple asynchronous design styles, the quasi delay insensitive (QDI) stands out for its robustness to delay variations. When coupled to DI codes like m-of-n and to four-phase handshake protocols, the QDI style produces the dominant asynchronous template currently in use. This paper evaluates the use of the Return-to-One 4-phase handshake protocol on Delay-Insensitive Minterm Synthesis (DIMS) logic blocks. Results point that this protocol leads to significant reductions on power consumption when compared to classic Return-to-Zero protocols. No extra hardware is required by the evaluated protocol, as the only required modification is that OR gates are replaced by AND gates, adding no extra delay to the resulting circuit. [ABSTRACT FROM PUBLISHER]

This demonstration presents the use of the Library Characterization Environment (LiChEn) for characterizing asynchronous standard cells. The tool was employed for the electrical characterization of a library with over five hundred asynchronous standard cells. In this work, a case study of a fundamental asynchronous component, the C-Element, will be presented to validate the use of the tool. LiChEn was designed due to the necessity of automating the process of characterizing asynchronous standard cells. Albeit this task can be done with tools from industrial EDA vendors, the use of these proved to require laborious manual work. These tools were designed for characterizing standard cells for synchronous systems and usually fail to recognize complex asynchronous logic. Moreover, asynchronous components are not available off the shelf in typical standard cell libraries, which constrains the asynchronous paradigm for full-custom approaches. As asynchronous techniques gain relevance in the research community, LiChEn can present a practical solution for a wider adoption of such techniques, by allowing an automated characterization of asynchronous standard cells. [ABSTRACT FROM PUBLISHER]