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In the digital age, medical images have become an indispensable tool for the diagnosis of certain diseases and health prevention. In the face of increasing computing power and diverse means of attack, as well as the need for real-time processing of medical images, traditional encryption and watermarking techniques may no longer be sufficient to effectively protect the integrity and copyright of these sensitive images. Based on this practical requirement, this study proposes a novel digital watermarking algorithm for copyright authentication of ophthalmic medical images using a chaotic system. This algorithm integrates a novel three-dimensional pupal equilibrium curved hyperchaotic system (PCHCS) to enhance the encryption effect of the AES algorithm. Clever embedding of watermarks in the edge regions of the ROI using Least Significant Bit (LSB) technology ensures minimal impact on diagnostic quality. RONI uses DCT transform for processing to enhance copyright authentication. The chaotic system and watermarking algorithm have been implemented on FPGA to further demonstrate their feasibility. The PSNR of the proposed system can reach more than 55 dB and the SSIM value is close to 1. The values of NC and BER also perform well under various attacks. Experimental results show that the designed watermarking algorithm has good invisibility and robustness. [ABSTRACT FROM AUTHOR]

This paper describes observations and experiences collected during 14 years of running the "Integrated circuits" course in the framework of a distance learning program. The main objective of the "Integrated circuits" course is to raise the interest in microelectronics, convince the students that IC design is not a "secret science" requiring extraordinary talent and prepare the students for continuation toward M.Sc. degree. The course includes a mixture of teaching materials available online for self-studying, short video files, interactive self-tests, two "hands on" exercises and educational software needed for these exercises. E-mail and/or phone consultations, face-to-face or online meetings with the instructor are possible. About 1/3 of all students enrolled for the distance learning course perceive the "Integrated circuits" course as interesting, praise the design exercises and ask if it would be possible to continue education in microelectronic design at a more advanced level. Unfortunately distance learning at advanced level is not possible, mainly because professional design software can be used only on site, not remotely. [ABSTRACT FROM AUTHOR]

Currently, design and application of discrete memristor aroused much interests. In this paper, digital integrated circuits of discrete memristive systems are designed based on the proposed fixed-point specific processor with acceleration instructions. The discrete memristor and the discrete memristive chaotic map are designed based on the trigonometric function including the Sine function and the Cosh function. It shows that the chaotic system has rich dynamics and can generate hyperchaos. To design a universal digital integrated circuit implementation method, a fixed-point specific processor is designed which is programmable. As a result, the chip layout of the memristive systems is obtained. Numerical simulations are completed in accordance with the Matlab simuation results. Compared with the ASIC(Application-Specific Integrated Circuit) based method, the digital circuit in this paper is two times larger in area and has 50% more power consumption due to the trigonometric and hyperbolic functions, but it can be reprogrammed to implement different models. It provides a new technical scheme for the application of discrete memristors in different engineering application fields. [ABSTRACT FROM AUTHOR]

The feedthrough effect can significantly affect the performance of MEMS gyroscopes and even lead to device failure. In order to address the inevitable problem of feedthrough capacitance caused by microfabrication process and circuit structure, two automatic feedthrough cancellation solutions are proposed based on the analysis of the feedthrough effect. Firstly, an equivalent feedthrough model is established for MEMS gyroscopes. Then, through theoretical derivation and model simulation, various influences of feedthrough effect are analysed, and the critical value of feedthrough capacitance is calculated to achieve better compensation effects. For feedthrough capacitance greater than the critical value, a feedthrough cancellation method utilizing AD5231 digital potentiometer for generating an inverse signal is designed. For the situation of feedthrough capacitance less than the critical value, a feedthrough cancellation method based on pure digital circuit calculation is proposed. The experimental results show that the method of utilizing digital potentiometer effectively reduces the feedthrough level from −17.46 dB to −32.75 dB, and the method of utilizing pure digital circuit calculation compensates the feedthrough signal of 100.04 mV to almost zero (2.44 mV) within the range of ADC sampling accuracy. These two methods can accurately and quickly suppress feedthrough signal to improve the detection performance of MEMS gyroscopes, and are expected to meet the needs of future mass production. In addition, they can be widely applied to various MEMS devices that require feedthrough cancellation. [ABSTRACT FROM AUTHOR]

Basic analog–digital motion detection circuits with low power consumption were proposed based on the vertebrate retina. The motion sensor based on the retina is constructed with a one- or two-dimensional array of the unit circuits. The proposed unit circuit for motion detection is constructed with an analog circuit for photoelectric conversion and the digital circuit for generating the motion signal. The metal oxide semiconductor (MOS) transistors utilized to the analog circuits are operated in the subthreshold region. The analog circuit has the characteristic of the low power consumption. The proposed circuit was evaluated by the simulation program with integrated circuit emphasis (SPICE) with the 0.6 μm complementary metal oxide semiconductor (CMOS) process. The test circuits of basic digital circuits were fabricated with the same process. In the simulation and the experiment, the power supply voltage was set to the low voltage. We found that the digital circuit becomes low power consumption because the MOS transistors was operated in the subthreshold region by setting the low voltage. The proposed circuit is characterized by the simple structure and the low power consumption. In the future, the novel motion detection sensor with low power consumption can be realized by applying the integrated circuits constructed with the array of the proposed unit circuits. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps. [ABSTRACT FROM AUTHOR]

The multiplier circuit is considered to be a significant component of larger circuits, such as the arithmetic and logic unit (ALU), and it is crucial to enhance its energy efficiency. This objective can be easily achieved by utilizing graphene nanoribbon field-effect transistor (GNRFET) devices and adopting ternary logic. Ternary circuit designs demonstrate superior energy efficiency and occupy less space compared to binary ones. The adjustability of the threshold voltage (Vth) in GNRFET devices is directly influenced by the width of the graphene nanoribbon (GNR). This offers significant advantages for ternary circuit designs. This paper presents a 24-transistor low-energy GNRFET-based single-trit ternary multiplier. Our proposed design incorporates an enhanced voltage division technique to achieve logic ‘1’ while minimizing power consumption. The primary design approach employed in our design involves the utilization of unary operators and specialized transistor configurations to reduce the number of transistors and shorten the critical path. We used the Hewlett simulation program with integrated circuit emphasis (HSPICE) and GNRFET technology with a 32- nm channel length operating at 0.9 V and 300˚ K to evaluate the efficiency of our circuit. We then compared it with similar existing ternary multiplier circuits. The suggested circuit displays favorable delay and power consumption characteristics and ranks as the second most optimal design in terms of energy efficiency. Furthermore, it improves the energy-delay-product by at least 2.80%. [ABSTRACT FROM AUTHOR]

A hydrogen maser is a high-precision time measurement instrument with high frequency stability and low frequency drift, which is widely used in satellite navigation, ground time keeping, frequency measurement, and other fields. An active hydrogen maser (AHM) is better than the current space passive hydrogen maser (PHM) in orbit in terms of its frequency stability and drift rate, but it has the disadvantages of large volume and weight. To further reduce the volume and weight of the circuit, this paper demonstrates a digital circuit control system based on a field-programmable gate array (FPGA). It uses digital temperature control, digital detectors, digital down-conversion, digital phase-locked loops, and other digital methods for temperature control, cavity auto-tuning, and crystal phase locking, which improve the integration and flexibility of the circuit system. Meanwhile, a tuning method based on hydrogen flow is proposed, which effectively solves the problem of fluctuations in hydrogen maser resonance frequency with changes in the external environment. Our experimental results show that the designed digital circuit control system meets the requirements of an oven-controlled crystal oscillator (OCXO) loop and a cavity loop. Its frequency stability can reach 2.6 × 10 − 13 / 1   s and 1.4 × 10 − 15 / 10,000   s , which is close to the stability index of ground active hydrogen maser. This scheme has certain practical engineering value, and can be used in the design of hydrogen masers for next-generation space navigation satellites, deep space exploration, and space stations. [ABSTRACT FROM AUTHOR]

To meet the high dynamic voltage or current range measuring in real-time in the modern electrical industry, ranging from the surface science to non-destructive testing, this paper reports two broad dynamic ranging, universal, and compact digital lock-in amplifier methods for the huge dynamic range signal, termed as the hybrid and all-digital amplifiers. Both have reduced the complex components required in the traditional amplifiers to only two or three components without sacrificing the measuring accuracy, even by less than 0.05% in some situations, which has been evaluated via simulations and experiments with the FPGA circuit. Additionally, benefiting from the single-power supply strategy, the proposed methods are suitable for portable devices, including the pocket spectrometer, mechanical resonator monitor, and powered on battery. Such results in this paper illustrate the phase coherent technology with a compact, universal, and integrated circuit with a promising future. [ABSTRACT FROM AUTHOR]

Novel basic analog–digital edge detection circuits in this research were proposed based on the vertebrate retina. The vertebrate retina is a pre-processor for image processing in the brain and has superior functions such as edge detection and motion detection. The proposed circuit was evaluated by the simulation program with integrated circuit emphasis (SPICE) with the 0.6 μm complementary metal oxide semiconductor (CMOS) process. The simulation results with SPICE showed that the proposed circuits can operate normally. The test integrated circuit of the unit circuit was fabricated with a 0.6 μm CMOS process. The measured results showed that the unit circuit can detect the edge position. The test integrated circuits of one-dimensional array of unit circuits were fabricated with the same process. The measured results showed that the one-dimensional circuits can detect the edge position. In the future, the realization of a new vision sensor can be expected using the proposed circuit. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this work, a digital circuit for fast scan voltammetry (FSV) was developed based on dual-frequency method. It consists of six main modules including the microcontroller unit, signal generator module, solution resistance measurement module, ohmic drop automatic compensation module, keying module and display module. By online measuring the solution resistance without any interference from capacitive impedance first, the ohmic drop compensation could be precisely carried out, bringing reliable FSV detection. RC dummy cell, dummy cell with pseudo-Faradaic impedance and actual electrochemical cell were used to verify the performance of automatic ohmic drop compensation. Results show that, FSV could be performed using a conventional electrode with the scan rate up to 2400 V/s. And, a handheld device was manufactured with a weight of 100 g and a size of 9 × 6 × 3 cm, costing only $35. It provides a simple, reliable and stable FSV plateau for electrochemical detection. [ABSTRACT FROM AUTHOR]

Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or genome data to all the embryonic cells makes each cell capable of selecting required cell function using selective gene. The primary digital circuits of avionics are implemented on the fabric, where the configuration data in Cartesian Genetic Programming (CGP) format is evolved through customized GA. The CGP format is preferred over LUT format for the circuit configuration data due to its fixed data size in case of modular design. Further the CGP format enables fault detection at embryonic cell level as well as logic gate level. The various combinational and sequential circuits like adder, comparator, multiplier, register and counter are designed and implemented on embryonic fabric using Verilog. The circuit performance is evaluated using simulation. The proposed PHsClone genetic algorithm (GA) design with parallel-pipeline approach is to achieve faster convergence. Four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator. [ABSTRACT FROM AUTHOR]

The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. Vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expressions of logic, which require algorithmically complex calculators, are replaced by output state vectors of elements and digital circuits, focused on the parallelism of register logical procedures on regular data structures. A vector-deductive method for formula synthesis for propagating input lists (data) of faults is proposed, which has a quadratic computational complexity of register operations. A new matrix of deductive vectors has been synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read-write transaction in memory, elimination of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on technological solving all problems of technical diagnosis. In the work, the transition to vector logic in the organization of computing and the elimination of traditional logic presented in the form of tables and analytical expressions were carried out. The use of read-write transactions on memory in the absence of a command system focuses the new vector-logic computing to-wards deterministic quantum architectures based on stable subatomic memory particles. [ABSTRACT FROM AUTHOR]

The quantum-dot cellular automata computing paradigm shows particular promise in terms of density and power and also enabling a new approach to implement reversible computing. In this paper, we explore the efficient designs of various latches based on reversible logic for quantum-dot cellular automata building blocks, while applying the cell placement constraints introduced by the use of wave clock. Compared to previous literature, the proposed solutions show smaller cell count while using a potentially implementable clocking scheme for molecular QCA wave clocking. The functional correctness of the proposed latches are presented and verified using QCADesigner and HDLQ. Furthermore, we present detailed characterization and analysis, considering different cost metrics of the proposed latches. It is shown that, compared to previous literature, critical paths are decreased by 50%, 33%, 50%, 25% respectively for D-Latch, T-Latch, JK-Latch, and SR latch. There is also an improvement in timing is about 50% for D-Latch and JK-Latch, and 25% for SR-Latch. [ABSTRACT FROM AUTHOR]

In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson's equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator. [ABSTRACT FROM AUTHOR]

In real-time applications, unpredictable random numbers play a major role in providing cryptographic and encryption processes. Most of the existing random number generators are embedded with the complex nature of an amplifier, ring oscillators, or comparators. Hence, this research focused more on implementing a Hybrid Nature of a New Random Number Generator. The key objective of the proposed methodology relies on the utilization of True random number generators. The randomness is unpredictable. The additions of programmable delay lines will reduce the processing time and maintain the quality of randomizing. The performance comparisons are carried out with power, delay, and lookup table. The proposed architecture was executed and verified using Xilinx. The Hybrid TRNG is evaluated under simulation and the obtained results outperform the results of the conventional random generators based on Slices, area and Lookup Tables. The experimental observations show that the proposed Hybrid True Random Number Generator (HTRNG) offers high operating speed and low power consumption. [ABSTRACT FROM AUTHOR]

In this paper, a two-wing chaotic system is transformed into a four-wing chaotic system and an eight-wing chaotic system using fractal processing and the dynamic characteristics of new multi-wing chaotic systems are analyzed. The encryption of the image is accomplished by combining the eight-wing chaotic system and the improved AES algorithm. The number of AES encryption rounds is reduced to make it more suitable for image encryption. To further improve the encryption efficiency, the chaotic system circuit and AES parallel computation are designed and implemented on FPGA. Finally, the high performance of the chaotic system is demonstrated by the satisfactory encryption effect. This methodology provides a promising direction for the study of real-time image encryption. [ABSTRACT FROM AUTHOR]

Summary: In advanced technology, static random‐access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high‐energy particle strikes, which cause soft‐error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation‐hardened read‐decoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read‐decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02×/1.06×/1.07×/1.08× over NS10T/RHD12T/PS10T/RHBD10T at VDD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single‐event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. [ABSTRACT FROM AUTHOR]

In this paper, a new fundamental cell in positive feedback source coupled logic is presented, which is an improvement over the existing fundamental cell employed in digital circuit design in various high resolution mixed-signal integrated circuits. The operation of the existing fundamental cell relies on using large sized transistor in its centre branch, resulting in significantly larger implementation area. The proposed fundamental cell incorporates multi-threshold transistor in the center branch thereby allowing designer to use reduce its dimension and hence the area. The impact of the proposed modification is examined by configuring the cell as two input exclusive OR (XOR2) gate. The behaviour is analysed in terms of static and propagation delay parameters which are modelled and a design procedure is also elaborated. The theoretical prepositions are verified by designing and simulating for various operating conditions using model parameters of 180 nm CMOS technology node. A maximum error of 27% is observed between the simulated and predicted parameters. The process variation study through Monte Carlo analysis and PVT variations identifies the proposed fundamental cell based circuit as less prone to variations in comparison to existing fundamental cell based counterparts. A full adder, as an application of the proposed fundamental cell, shows a significant (66%) area reduction while delay, power and PDP are within 4% of their corresponding values for the existing one. [ABSTRACT FROM AUTHOR]

It is proposed to use transistor-transistor logic (TTL) for future fast, low-power digital electronic circuits. A relaxation quantum transistor can be the basic element of these circuits. This approach allows us to circumvent the difficulties of using field effect transistors based on nanowires. [ABSTRACT FROM AUTHOR]

We examine the modes of intervention of global public intellectuals at times of crisis. In critical situations, public intellectuals take positions on matters that affect the societies they inhabit and, eventually, all humanity. To this end, they take advantage of the opportunities afforded by new communications technologies, establishing an important distinction between the "analog" intellectual (who relies on the slow time of books, opinion columns, and bookstores) and the "digital" intellectual who uses modern information and communications technologies. To study the activities of global public intellectuals and their political influence, we propose to leave aside the notion of "transnational intellectual field" in favor of an understanding of a transnational intellectual stage peopled by a certain type of intellectual agent whose symbolic and cultural production is disseminated through a digital global public circuit. To illustrate the functioning of a circuit of this type, we take the example of the Project Syndicate platform. [ABSTRACT FROM AUTHOR]

The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis. This article is categorized under:Algorithmic Development > Structure DiscoveryTechnologies > Machine LearningTechnologies > Prediction [ABSTRACT FROM AUTHOR]

A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are investigated. Separate test regions are identified for each wearout mechanism. Two digital circuits, an 8-bit fast Fourier transform (FFT) circuit and a Leon3 microprocessor are used to demonstrate the capability of the framework. The lifetimes of standard cells are combined to compute the circuit lifetime, by combining the Weibull distributions that characterize the lifetime distribution of each of the standard cells. The errors in estimating wearout parameters consist of two parts: the error in estimating the wearout parameters at accelerated test conditions and the forecasting accuracy at use conditions. By estimating the errors in wearout parameters at accelerated test conditions, the optimal accelerated test region is found by determining the test conditions producing a minimal error. Test conditions are selected by minimizing the error at use conditions. Given a forecasting error target, the required sample size at each test condition is found. This work also considers the impact of variation in circuit size, type, and process parameters on the selection of optimal test conditions. [ABSTRACT FROM AUTHOR]

This article proposes a new necessary condition and the corresponding speedup strategies to the threshold function (TF) identification problem. The state-of-the-art to this identification problem could be very time-consuming when the function-under-identification is a non-TF with the unateness property. The proposed new necessary condition can be seamlessly integrated into this identification algorithm. As compared with the state-of-the-art, the improved identification algorithm with the proposed necessary condition can more effectively and efficiently detect non-TFs. Furthermore, according to the experimental results, the ratio of CPU time overhead in the process of checking the proposed necessary condition for identifying all the 8-input TF is only 0.1%. [ABSTRACT FROM AUTHOR]

With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz. [ABSTRACT FROM AUTHOR]

Copyright of Experimental Technology & Management is the property of Experimental Technology & Management Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper extends the concept of Karnaugh map from a logical function to a logical system, thereby allowing both the state transition graph and state transition matrix of a logical system, as well as a digital circuit, to be constructed directly. It is found that the Karnaugh map of a logical system is actually a two-dimensional state transition table or, equivalently, a table-like state transition graph and is also a grid-type state transition matrix. For constructing the state transition graph and state transition matrix of a logical system, the computational complexities of the methods based on the proposed Karnaugh map are exponentially lower than those of the existing methods. The Karnaugh maps of logical systems are then used in the analysis and design of clocked sequential circuits and in the simplification of multioutput gate circuits. Some illustrative examples and simulations are presented to demonstrate the results and their applications. [ABSTRACT FROM AUTHOR]

In general, existing logic synthesis methods for majority logic are limited to 3-input gates (maj-3). However, since majority gates with larger fan-in have been proposed for different emerging nanotechnologies, it has become important to consider such gates in the synthesis process. This paper proposes a novel majority logic synthesis flow where the gates can have an arbitrary number of inputs. The proposed approach is based on the relationship between majority and threshold logic functions. The proposed methods obtain an average reduction of 10% on the number of nodes when compared to a previous work that uses both maj-3 and maj-5 gates. When compared to the previous maj-3 synthesis, the average reduction on number of nodes is 14%. [ABSTRACT FROM AUTHOR]

Copyright of Experimental Technology & Management is the property of Experimental Technology & Management Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Experimental Technology & Management is the property of Experimental Technology & Management Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In the present research, we explore the possibility of utilizing a hardware-based neuromorphic approach to develop a tactile sensory system at the level of first-order afferents, which are slowly adapting type 1 (SA-I) and fast adapting type 1 (FA-I) afferents. Four spiking models are used to mimic neural signals of both SA-I and FA-I primary afferents. Next, a digital circuit is designed for each spiking model for both afferents to be implemented on the field-programmable gate array (FPGA). The four different digital circuits are then compared from source utilization point of view to find the minimum cost circuit for creating a population of digital afferents. In this way, the firing responses of both SA-I and FA-I afferents are physically measured in hardware. Finally, a population of 243 afferents consisting of 90 SA-I and 153 FA-I digital neuromorphic circuits are implemented on the FPGA. The FPGA also receives nine inputs from the force sensors through an interfacing board. Therefore, the data of multiple inputs are processed by the spiking network of tactile afferents, simultaneously. Benefiting from parallel processing capabilities of FPGA, the proposed architecture offers a low-cost neuromorphic structure for tactile information processing. Applying machine learning algorithms on the artificial spiking patterns collected from FPGA, we successfully classified three different objects based on the firing rate paradigm. Consequently, the proposed neuromorphic system provides the opportunity for development of new tactile processing component for robotic and prosthetic applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches. [ABSTRACT FROM AUTHOR]

Copyright of Research & Exploration in Laboratory is the property of Research & Exploration in Laboratory and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits. Both traditional CMOS and the state-of-art FinFET technology are taken into consideration. A circuit’s lifetime distribution depends on its usage and the resulting temperature profile. Emulation of the circuit operation extracts the relevant usage parameters. These parameters are converted to state probabilities at the inputs of the standard cells. The lifetime distributions of standard cells are characterized by taking into account all possible input state probabilities and die-to-die process variations. Because MOL TDDB depends on the layout, a step involved in estimating the lifetime distributions of standard cells is the analysis of the layout for MOL TDDB. Two different methods to extract the layout features are presented for traditional CMOS and FinFET technologies. By precharacterizing the standard cell lifetime distribution, our simulator can find the lifetime limiting cells in a circuit, and thus, circuit designers can replace such cells with a combination of standard cells with a longer lifetime to make the circuit more robust. The results also indicate that we need to pay more attention to the newly emerging MOL TDDB when designing new standard cells for FinFET technology. [ABSTRACT FROM AUTHOR]

Recent papers have shown that the circuit design based on complex gates generated under demand became a valuable alternative to surpass the well-known standard cell approach, especially for critical parts of digital systems, which contains a high restrictive specification level. Through this strategy, it is possible to minimize the number of transistors, potentially optimizing the circuit in electrical and geometrical domains. On the other hand, this paradigm is limited considering the increasing complexity of digital systems and its dependence on the circuit designer. In this scenario, we propose the Libra methodology, an automatic approach for the design of CMOS complex logic gates. Libra is based on a transistor network generation paradigm capable to deliver solutions with diversified topologies. Furthermore, it has a flexible gate sizing methodology and a layout generation process under demand, which includes automatic placement, routing, and compaction. Besides that, it implements on-the-fly validation, verification and test routines. This way, it is possible to compare our tool with the widely used method for complex gate design. Experiments have shown that Libra can deliver optimized cells in terms of area and delay relative to the solutions obtained from the usual Boolean factoring paradigm. [ABSTRACT FROM AUTHOR]

adder block is one of the major block in circuit design. inserting efficient adder block will cause having more efficient final design. In this paper improved GDI based adder will be designed. Proposed GDI based adder is more efficient compared to [2] and [4] in delay, performance and PDP. at last an adder/subtractor circuit will be designed. [ABSTRACT FROM AUTHOR]

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and image processing. [ABSTRACT FROM AUTHOR]

Recently demonstrated CMOS circuits based on Ge nanowires (Ge-FET) promise sustained technology scaling because higher mobility Ge guarantees target ${I}_{\text {ON}}$ at a lower ${V}_{{\textit {DD}}}$. Unfortunately, this promise is counterbalanced by the fact that Ge is a poor thermal conductor, thus, the thermal confinement of the surround-gate topology may exacerbate self-heating (SHE) and erode the intrinsic performance gain associated with the high channel mobility. In this paper, we use: 1) electrical and optical methods to, respectively, characterize channel and surface SHE of Ge-FET with various channel lengths ( ${L}_{\text {ch}}$ ), widths ( ${W}_{\text {ch}}$ ), and the number of the nanowires (NWs) (#NW); 2) interpret the results obtained by the 3-D thermal modeling, and compare theoretically the SHE in Ge-FET configured in various topologies, such as bulk FinFET, silicon-on-insulator FinFET, and gate-all-around NW-FET; and 3) embed the results in an electrothermal SPICE simulator to compare the performance of ring oscillators based on Ge-FET and Si-FET. Our results show that the existing Ge-FET (with an airgap) is thermally suboptimal, but once optimized, SHE in Ge-FET would be comparable to that of Si-FET. The results encourage sustained development of Ge-FETs. [ABSTRACT FROM AUTHOR]

In this paper, a straightforward and effective method to identify threshold logic function (TLF) is presented. Threshold logic is a promising alternative to conventional Boolean logic due to its suitability for emerging technologies, like memristors, quantum-dot cellular automata, resonant tunneling device, and spintronic devices. Identification and synthesis of TLF are essential tasks in a design flow based on such a logic strategy. The proposed method relies on irredundant sum-of-products Boolean function description form and exploits both ordering of variables and system of inequalities to assign the variable weights and the function threshold value. This is the first heuristic algorithm able to identify all threshold functions with up to six variables, being also more effective than other heuristic methods for functions with a larger number of variables. For functions obtained from k -cuts of benchmark circuits, experimental results demonstrated effectiveness near to 100% when compared to exact methods, even when the number of function variables increases. The execution time of the proposed approach is similar to related heuristic methods, being faster than integer linear programming-based algorithms. [ABSTRACT FROM PUBLISHER]

The authors propose an on‐chip wear‐out monitoring technique, which is based on monitoring the environmental conditions experienced by a digital circuit. The frequency of the T‐sensitive ring oscillator (RO) emulates the wear‐out stress strength caused by the temperature conditions based on the model of exponential dependence of the stress on the inverse of temperatures. The frequency of the VT‐sensitive RO emulates the stress due to time‐dependent dielectric breakdown, which is stressed by voltages as well as temperatures. Thus, the accumulated counts driven by the ROs directly indicate the total wear‐out stress that the product has experienced so far. The measured results of a test chip fabricated by 28 nm High‐k Metal Gate process confirm the expected dependence of T‐/VT‐sensitive RO frequencies on temperatures and voltages, enabling the emulation of wear‐out. The methodology is presented to estimate the stress amount of various wear‐out factors having different thermal activation energies. The proposed wear‐out stress monitor would make automotive microcontrollers more reliable when they operate at boosted voltages and elevated temperatures to meet performance requirements of cutting‐edge applications such as advanced driver assistance systems. [ABSTRACT FROM AUTHOR]

The AIM2-ASC inflammasome is a filamentous signaling platform essential for mounting host defense against cytoplasmic dsDNA arising not only from invading pathogens but also from damaged organelles. Currently, the design principles of its underlying signaling network remain poorly understood at the molecular level. We show here that longer dsDNA is more effective in inducing AIM2 assembly, its self-propagation, and downstream ASC polymerization. This observation is related to the increased probability of forming the base of AIM2 filaments, and indicates that the assembly discerns small dsDNA as noise at each signaling step. Filaments assembled by receptor AIM2, downstream ASC, and their joint complex all persist regardless of dsDNA, consequently generating sustained signal amplification and hysteresis. Furthermore, multiple positive feedback loops reinforce the assembly, as AIM2 and ASC filaments accelerate the assembly of nascent AIM2 with or without dsDNA. Together with a quantitative model of the assembly, our results indicate that an ultrasensitive digital circuit drives the assembly of the AIM2-ASC inflammasome. [ABSTRACT FROM AUTHOR]

Neuron models are available for computational neurodynamics and the main dynamical properties can be reproduced in the numerical scheme for further dynamical analysis. During model setting, some important biophysical factors should be considered and thus reliable neuron models can be approached. In this paper, a neuron model driven by autapse connection is investigated with the effect of electromagnetic induction being considered as well. A digital neuronal circuit is designed by using FPGA, the dynamical response and biological function of autapse connection. It is found that positive feedback in autapse can modulate the oscillating behaviors in the digital circuit, which could be effective for further investigation on digital neuronal network. [ABSTRACT FROM AUTHOR]

This paper describes a digital frequency multiplier for a pulse rate. The multiplier is based on the recursive processing of the input and output periods and their time differences. Special emphasis is devoted to the techniques which provide the development of multipliers based on this principle. The circuit is defined by two system parameters. One is the ratio of two clock frequencies and the other is a division factor of a binary counter. The realization of the circuit is described. The region of the system parameters for the stable circuit is presented. The different aspects of applications and limitations in realization of the circuit are considered. All mathematical analyses are made using a Z transform approach. It is shown that the circuit can be also used in tracking and prediction applications. Computer simulations are performed to prove the correctness of the math and the whole approach. [ABSTRACT FROM AUTHOR]

We propose a characterization methodology for random telegraph noise (RTN) based on gate delay measurement. To convert delay change to MOSFET threshold voltage fluctuation, \Delta VT , a topology-reconfigurable ring oscillator is utilized. We discuss the issue of detecting RTN-induced discrete fluctuations in the delay and develop a kernel density-based method to detect the fluctuations. Characterization results of several RTN properties from a test chip fabricated in a 65 nm bulk process are presented. Particular focus is given on the suitable distribution to present RTN-induced overall \Delta VT distribution and its gate area dependency. The results show that lognormal distribution is better at representing the total \Delta VT distribution. RTN-induced delay fluctuation of 40% has been observed for a single gate under weak inversion operation. Local process variation and RTN amplitude are found to be uncorrelated. The proposed methodology is thus suitable for characterizing RTN of devices operating under switching condition. [ABSTRACT FROM PUBLISHER]

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and image processing. [ABSTRACT FROM AUTHOR]

This paper describes a powerful digital time and/or phase shifter of pulse rates, based on Time Recursive Processing. It can function either as a time shifter or as a phase shifter. The circuit can generate precise shifting for a pulse rate with a constant input period, but it is also capable to shift a pulse rate whose period is a ramp function. Besides that, the shifter can be used in tracking and prediction applications. The shifter is described by recursive equations as a linear discrete system. All mathematical analyses are made using the Z transform. Computer simulations are employed to prove the correctness of the mathematical analysis. The realization of the shifter is described and, to demonstrate the shifter functioning, actual oscilloscope screenshots are presented. [ABSTRACT FROM AUTHOR]

The need for dependable digital circuitry with the capability to operate reliably in high-temperature environments has been increasing drastically in applications such as automobile, aerospace, oil exploration, and power electronics. However, wide temperature swings significantly alter the threshold voltage of individual transistors, which adversely affects circuit timing in traditional synchronous designs. Such timing changes may in turn violates the setup and hold times of the clocked components, leading to potential circuit failure. This paper presents a complex digital integrated circuit design methodology using both synchronous and asynchronous logic for comparison in a young silicon carbide (SiC) design process developed by Raytheon UK. Seventeen circuits were designed, fabricated, and tested with results showing correct operation at temperatures at and above the target temperature of 300 °C. [ABSTRACT FROM PUBLISHER]

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series–parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches. [ABSTRACT FROM AUTHOR]