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In this study, we conduct a comparative analysis of single-beam laser annealing (SBLA) and dual-beam laser annealing (DBLA) techniques for semiconductor manufacturing. In the DBLA approach, two laser beams were precisely aligned to simultaneously heat a phosphorus-doped silicon (Si) wafer. The main objective was to investigate the impact of the two annealing techniques on the electrical properties, crystalline structure, and diffusion profile of the treated phosphorus-doped Si at equivalent laser powers. Both SBLA and DBLA improved the electrical properties of the phosphorus-doped Si, evidenced by increased carrier concentration and reduced carrier mobility. Additionally, the crystalline structure of the phosphorus-doped Si showed favorable modifications, with no defects and improved crystallinity. While both SBLA and DBLA produced similar phosphorus profiles with no significant redistribution of dopants compared to the as-implanted sample, DBLA achieved a higher activation ratio than SBLA. Although the results suggest improved dopant activation with minimal diffusion, further studies are needed to clearly confirm the effect of DBLA on dopant activation and diffusion. [ABSTRACT FROM AUTHOR]

As gallium oxide-based heterojunction devices gain prominence, low-resistance contacts to aluminum gallium oxide material are of increasing importance for high performance and access to modulation doped layers. Here, the activation of ion-implanted silicon donors is investigated as a function of donor density from 5 × 1018 cm−3 to 1 × 1020 cm−3, activation anneal duration from 6 s to 600 s, and activation temperature from 900°C to 1140°C. Importantly, ohmic behavior was achievable across a reasonably wide process window at moderate to high doping concentrations. Specific contact resistance of 1 × 10−3 Ω cm2 and sheet resistance of 2.8 kΩ/□ were achieved for a 60 nm-deep 1 × 1020 cm−3 box implant after activation at 1000°C for 6 s with standard Ti/Au contacts. Under these conditions, an activation efficiency of 7% was observed with Hall mobility of ~32 cm2/Vs. Furthermore, we demonstrate a Schottky diode formed of implanted material with a rectification ratio > 106 and further confirm the Hall carrier density results using capacitance–voltage profiling analysis. Finally, we show the significant impact of anneal duration and the potential for deleterious over-annealing which reduces the active carrier density, mobility, and resultant material conductivity. [ABSTRACT FROM AUTHOR]

Carrier (electron) compensation is an important issue in impurity (donor) doped ZnO thin films, which must be understood to achieve the desired electrical conductivity. Unprecedentedly, using trivalent Al, tetravalent Ti, and pentavalent Vanadium, (the atomic symbol is not used to avoid confusion with the conventional vacancy symbol) metal ion doping in ZnO thin films while keeping all the growth and annealing parameters similar, we demonstrate that donor–acceptor (D-A) compensation in the doped film is influenced largely by the dopant valence. Hall data show a drastic decrease in the conductivity and carrier concentration values indicating progressively more D-A compensation as the dopant valence increases. Post-growth annealing in special ambient recovers trapped free carriers due to dopants' activation. The activation of the dopants due to annealing in Ar + 10% H2 + excess Zn ambient is far more than that happened in only Ar + 10% H2 ambient. To support this, we further discuss the dark and photo-Hall electrical transport data of the as-grown and annealed films measured under sub-bandgap photo-excitations to release the electrons from the acceptor-like complexes. [ABSTRACT FROM AUTHOR]

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry. [ABSTRACT FROM AUTHOR]

The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices. [ABSTRACT FROM AUTHOR]

Laser thermal annealing (LTA) has played an important role in the fabrication of scaled semiconductor devices by reducing the heat budget of the dopant activation process. During the laser annealing of entire wafer areas, the beam scanning pattern and overlap ratio have significant effects on uniform heating during the process. In this study, a numerical simulation of the LTA process was carried out using a three-dimensional transient heat transfer model. The temperature distribution produced by different laser scan paths and beam overlap ratios was analyzed. Additionally, the behavior of the dopant (phosphorus) diffusion induced under the multipath and beam overlapping conditions was numerically investigated. According to the simulation result, a zig-zag pattern generated hot spots around the corner areas of the beam path due to the greater heat accumulation per unit area; however, a bidirectional pattern induced cold spots due to the absence of laser heating around the corner areas. It was also found that the maximum temperature reachable in the beam overlapped region was much lower than that obtained along the beam scanning path, and the most uniform heating could be obtained when the zig-zag pattern and a 50% overlap ratio were used. According to the dopant diffusion and concentration distribution predicted for the case of the zig-zag pattern and 50% overlap ratio, the difference in the dopant diffusion length was approximately thirty times within the scanned area. [ABSTRACT FROM AUTHOR]

In this brief, we demonstrate the gate-first HfZrO2 (HZO) fully depleted silicon-on-insulator (FDSOI) negative capacitance field-effect transistor (NCFET) with self-aligned nickel-silicide (NiSi) source and drain (S/D). Although the gate-first process has advantages in terms of fabrication simplicity, the dopants of S/D cannot be fully activated since the polarization of ferroelectric HZO film is seriously degraded at high temperatures. To improve the S/D resistance without the polarization degradation, self-aligned S/D nickel silicidation, which induces dopant activation and dopant segregation at relatively low temperature, was simultaneously performed during ferroelectric post metal annealing (PMA). It is experimentally confirmed that 1) high concentrated dopants (As+) can be fully activated during silicidation through diode measurements and 2) S/D resistance can be reduced by NiSi silicidation through resistance measurements. Furthermore, it is verified that the electrical characteristic of NCFET with NiSi S/D exhibits superior current drivability without subthreshold swing (SS) degradation compared with that of NCFET without NiSi. [ABSTRACT FROM AUTHOR]

Electrical properties and microstructure of phosphorus (P) implanted p-type Si substrates were evaluated by four-point probe (4PP), Differential Hall Effect Metrology (DHEM), secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM) techniques, after RTA 750–950°C and CO2 laser 120–140W annealing. When RTA temperature was increased, defect concentration at a-Si/c-Si interface gradually disappeared. For CO2 laser annealing, defects were found to aggregate at the end of range (EOR) region. Sheet resistance (Rs) values decreased significantly with increasing RTA temperature due to defects disappearing at EOR. Rs did not change appreciably for the CO2 laser annealing case. The dopant activation ratio was less than 50% below RTA temperature of 850 °C, and it increased to 70% at 950 °C. For CO2 laser annealing, the activation ratio could reach to over 80% regardless of the laser power. The highest active concentration and the lowest resistivity or mobility were found to be within the top 20 nm region of the surface. Although RTA annealing conditions influenced dopant diffusion and the resulting electrical property depth profiles significantly, depth profiles did not change much with changes in CO2 laser power level. It was demonstrated that DHEM data in conjunction with SIMS and TEM data can be successfully employed to evaluate, in detail, the electrical properties of ultra-shallow junctions for metal oxide semiconductor field effect transistor (MOSFET) applications. [ABSTRACT FROM AUTHOR]

Organic doping is widely used for defining the majority charge carriers of organic thin films, tuning the Fermi level, and improving and stabilizing the performance of organic light‐emitting diodes and organic solar cells. However, in contrast to inorganic semiconductors, the doping concentrations commonly used are quite high (in the wt% range). Such high concentrations not only limit the scope of doping in organic field‐effect transistors (OFETs), but also limit the doping process itself resulting in a low doping efficiency. Here, the mechanism of doping at ultralow doping concentrations is studied. Doped C60 metal‐oxide‐semiconductor (MOS) junctions are used to study doping at the 100 ppm level. With the help of a small‐signal drift‐diffusion model, it is possible to disentangle effects of traps at the gate dielectric/organic semiconductor interface from effects of doping and to determine the doping efficiency and activation energy of the doping process. Doped C60 OFETs with an ultralow operation voltage of 800 mV and an excellent on/off ratio of up to 107 are realized. The devices have low subthreshold swing in the range of 80 mV dec−1 and a large transconductance of up to 8 mS mm−1. [ABSTRACT FROM AUTHOR]

In situ phosphorus‐doped epitaxial silicon films have attracted significant attention as source and drain materials because low specific contact resistivities have been achieved on such films by increasing the active carrier concentration using millisecond laser annealing. However, the active phosphorus concentration that can be achieved using millisecond laser annealing is much less than the incorporated concentration. To increase the activation efficiency, nanosecond laser annealing with a dwell time ≈104 times shorter than that of millisecond laser annealing is investigated and the diffusion, strain, microstructure, and electrical properties of single‐ and multipulse nanosecond laser‐annealed samples are examined. The melting depth simulation classifies the energy density regions and explains the limited diffusion in nanosecond laser annealing. After multipulse nanosecond laser annealing, more phosphorus is activated without diffusion than by millisecond laser annealing. Moreover, almost all the incorporated phosphorus atoms are activated by the nanosecond laser, which melts in situ phosphorus‐doped epitaxial silicon films without major strain loss. The increased active carrier concentration presents an opportunity to achieve low contact resistivity characteristics. [ABSTRACT FROM AUTHOR]

An N‐doped TiO2 model reveals a conceptually different mechanism for activating the N dopant based on delocalized orbital hybridization through O vacancy incorporation. Synchrotron‐based X‐ray absorption spectroscopy, time‐resolved fluorescence, and DFT studies revealed that O vacancy incorporation can effectively stimulate the delocalization of N impurity states through p‐band orbital modulation, which leads to a significant enhancement in photocarrier lifetime. Consequently, this effect also results in a remarkable increase in the incident photon‐to‐electron conversion efficiency in the range of 400–550 nm compared to that of conventional N‐incorporated TiO2 (15 % versus 1 % at 450 nm). This work reveals the fundamental necessity of orbital modulation in the band engineering of metal oxides for driving solar water splitting and beyond. [ABSTRACT FROM AUTHOR]

Germanium n+/p junctions with high phosphorus dopant activation (>1020 cm−3) and minimal dopant diffusion were achieved by $P$ implantation and laser spike annealing (LSA) at temperatures ≥794 °C for 400 \mu \text{s} . In addition, there is no evidence of any residual extended defectivity near the junction after LSA. The effect of F co-doping was also investigated, demonstrating the reduction in both diffusion and activation. The thermal stability and electrical characteristics of Ge n+/p junction activated by LSA were evaluated. [ABSTRACT FROM PUBLISHER]

BF+ implantation is used for the first time for the formation of source/drain (S/D) junctions in Ge MOSFETs. It offers a higher B activation level ( \sim 2.0\times 10^20 cm ^-3) and a shallower junction depth in Ge compared with B+ and BF2+ implantation for the same projected range, after rapid thermal annealing at 800 °C. Germanium pMOSFETs using BF+ implantation demonstrate a high ON/OFF ratio of \sim 10^7 and an enhancement of ON current, due to the reduction of S/D series resistance compared with B+ or BF2+ implanted junctions. [ABSTRACT FROM PUBLISHER]

The possibility of direct writing thin semiconductive channels and structures on insulating substrates in a clean room-free process is attractive for its simplicity, cost effectiveness, and possibility of a wide choice of substrates. A broad range of applications, such as large-area electronic devices (touch screens, flexible displays), sensors, or optical wave guides could benefit from such a process. In this work, we directly write on doped hydrogenated amorphous silicon (a-Si:H), with thickness in the range 10 nm-1 μm, using a Nd-YAG laser operating at 532 nm that is part of a Witec Raman confocal system. The contrast in conductivity between the exposed and unexposed areas is so high that the a-Si:H matrix needs not to be removed after exposure. B- and P-doped films were deposited on plastic, glass, and oxidized silicon wafers. The laser power threshold for crystallization was studied. The highest conductivity (886 Ω−1 cm−1) was obtained on wafer. On hard substrates, it is possible to tune the mesoscopic electrical conductivity in a very broad range of values (∼10−4-103) by design of the pattern to be transferred. Patterned films are piezoresistive with gauge factors as high as +18 and −29 for p - and n-type patterns, respectively. SEM image of laser written lines on a 10 nm thick a-Si:H film deposited on a Si/SiO2 substrate. Four regions are clearly distinguishable: the metal contact on the top area; the laser eroded area (lines); the crystallized areas adjacent to lines; the amorphous region at the bottom right. [ABSTRACT FROM AUTHOR]

We demonstrate Ge enhancement-mode nMOS FinFETs fabricated on 300-mm Si wafers, incorporating an optimized gate-stack (interface trap density D\mathrm{ it} below 2 \times 10^11 eV ^-1\cdot \mathrm cm^-2) , n+-doping (active doping concentration N\mathrm{ act} exceeding 1 \times 10^20~\mathrm cm^-3) , and metallization (contact resistivity \rho c below 2 \times 10^-7\Omega \cdot \mathrm cm^2) modules. A new circular transmission line \rho c extraction model that captures the parasitic metal resistance is proposed. At a supply voltage V\mathrm{ DD} of 0.5 V, 40-nm-gate-length FinFET devices achieved an ON-performance I\mathrm{\scriptscriptstyle ON} of 50 \mu \textA/\mu \textm at an OFF-state current I\mathrm{\scriptscriptstyle OFF} of 100 nA/ \mu \textm , a subthreshold swing S\mathrm{ sat} of 124 mV/decade, and a peak transconductance gm of 310 \mu \textS/\mu \textm . The same gate-stack and contacts were deployed on planar devices for comparison. Both FinFET and planar devices in this paper achieved the highest reported gm/S\mathrm{ sat} at V\mathrm{ DD} = 0.5 V to date and the shortest gate lengths for Ge nMOS enhancement-mode transistors. [ABSTRACT FROM AUTHOR]

Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550^\circC. Next, enhancing the substitutional carbon concentration ([C]sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated. [ABSTRACT FROM PUBLISHER]

Processes inducing micro- and nano-structural modifications of materials play a crucial role in the advanced technology. In particular, laser irradiation attracts a great interest as a tool for the localized thermal treatment (laser thermal annealing) when the global heating of the sample could be detrimental. With the expansion of the application fields, a research effort is required to understand the kinetics in systems subjected to extreme transient excitations induced by the interaction with the laser light. Modeling and simulations cover a relevant part of this research effort. In this paper we review the current status of the laser annealing modeling. The theoretical analysis will be restricted to the heating stage of the irradiation, i.e. the ultrafast energy transfer from the electronic states to the lattice vibrations will not be considered. Therefore, the timescale of the process must be larger than ∼1 ns. Models, numerical methods and applications to the experiments will be presented to deal with different questions. Among them: the simulation of the thermal field when the heat absorption depends consistently on the temperature, the prediction of a phase change kinetics in a melting process including the redistribution of alloyed systems, the damage evolution in the transient non-uniform thermal field promoted by the irradiation induced kinetics, the related dopant activation kinetics. Numerical techniques include: continuum, kinetic Monte Carlo and molecular dynamics approaches. [ABSTRACT FROM AUTHOR]

We propose a new strategy for in-situ observation of dopant activation process using scanning tunnelling microscopy (STM) technology. Two factor techniques are established within our original STM system combined with liquid-metal-ion-source ion-gun (LMIS-IG/STM): (1) in-situ real-time observation of Si(001)-2×1 surface modified with dopant ions, and (2) in-situ hydrogen passivation of Si(001)-2×1 surface. Sequential STM images of the surface morphological changes are successfully obtained with keeping the original observation area. The hydrogenated Si(001)-2×1 surface is stable enough even under the degraded vacuum conditions which are unavoidable in ion irradiation processes. (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

In this paper, the contact resistivity of NiGe on n-doped Ge is extracted. Although phosphorus is the slowest n-type dopant in terms of diffusion in Ge, the corresponding contact resistivity data for this dopant are sparse. Contact resistivity dependence on implant dose will be determined, as well as a comparison of phosphorus- and arsenic-doped Ge layers. The impact of high contact resistance is evaluated for future technology n-type metal–oxide–semiconductor germanium devices. [ABSTRACT FROM PUBLISHER]

Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) dopant activation of high-Ge-concentration SiGe channel MOSFETs with a high-k/metal gate stack. Flash annealing of SiGe channel pMOSFETs is shown to be an effective way to preserve channel integrity while achieving a low S/D resistance. Excellent mobility and short-channel device performance are realized. In addition, as the concentration of Ge in the SiGe layer is increased, high B activation can be achieved with a lower peak temperature Flash anneal. As a result, the sheet resistance of the implanted \p^+ junction can be comparable with that of higher temperature Flash-annealed (or optimal spike-annealed) Si. Furthermore, minimizing Ge diffusion reduces performance variation (such as statistical threshold voltage variation), which may be caused by the introduction and/or growth of defects in the strained SiGe heterostructure channel. It is shown that high-performance SiGe channel pMOSFETs with high Ge concentrations and a scaled high-k/metal gate can be achieved by a millisecond Flash-assisted RTA technique while preventing undesirable effects in the SiGe channel, such as within-wafer statistical performance variation. [ABSTRACT FROM PUBLISHER]

Off-axis electron holography has been used to measure the electrostatic potential profile across the p-n junction of an AIGaAs/GaAs light-emitting diode with linearly graded triangular AIGaAs barriers. Simulations of the junction profile showed small discrepancies with experiment when the nominal dopant concentrations of Si and Be impurities were used. Revised simulations reproduced the measurements reasonably using reduced dopant levels that reflected the efficiency of dopant activation. Band-edge diagrams simulated with the nominal and revised dopant concentrations were also compared in terms of the effect that activation efficiency had on the AIGaAs barrier shape and carrier transport. It is concluded that electron holography measurements combined with modeling offer device designers and growers a helpful tool for analyzing and confirming doping profiles in complex heterostructures. [ABSTRACT FROM AUTHOR]

A high-performance In0.53Ga0.47As n-channel MOSFET integrated with a HfAIO gate dielectric and a TaN gate electrode was fabricated using a self-aligned process. After HCI cleaning and (NH4)2S treatment, the chemical vapor deposition HfAlO growth on In0.53Ga0.47As exhibits a high-quality interface. The fabricated nMOSFET with a HfAIO gate oxide thickness of 11.7 nm shows a gate leakage current density as low as 2.5 × 10-7 A/cm2 at Vg of 1 V. Excellent inversion capacitance was illustrated. Silicon implantation was self-aligned to the gate, and low-temperature activation for source and drain was achieved by rapid thermal annealing at 600 °C for 1 mm. The source and drain junction exhibited an excellent rectifying characteristic and high forward current. The result of an In0.53Ga0.47As nMOSFET shows well-performed Id-Vd and Id-Vg characteristics. `The record high peak electron mobility of 1560 cm2 /Vs has been achieved without any correction methods considering interface charge and parasitic resistance. [ABSTRACT FROM AUTHOR]

The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the Ioff-Ion performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current. [ABSTRACT FROM PUBLISHER]

A metastable GeSi layer 265 nm thick was deposited pseudomorphically on a Si(100) substrate and then implanted with 100 keV phosphorus ions at room temperature for doses of 5 × 10/cm to 1.5 × 10/cm. The ions stop within the epilayer (projected range ∼125 nm). MeVHe backscattering/channeling spectrometry, transmission electron microscopy, and double-crystal x-ray diffractometry were used to characterize the damage and strain in the films. The samples were subsequently annealed in high vacuum from 400-800°C for 30 min at each temperature. For the nonamorphized samples (doses of 5 and 10 × 10/cm), most of the implantation-induced damage and strain disappear after annealing at 400-550°C, but the implanted P ions activate poorly. After annealing at 700-800°C, near complete activation is achieved but the strain relaxes. For the amorphized samples (dose of 1.5 × 10/cm), the amorphous GeSi regrows by solid-phase epitaxy and the dopants are ∼100% activated after annealing at 550°C, but the regrown GeSi relaxes with a high density of dislocations. The strain relaxes more extensively upon annealing in an implanted sample than in a nonimplanted one, other conditions being equal. This effect is more pronounced at higher ion doses, probably due to the increased amount of damage introduced at high doses. [ABSTRACT FROM AUTHOR]

We report high performance Ge p+/n junctions using a single, cryogenic (−100 °C) boron ion implantation process. High activation \(> 4\times 10^{20}\) cm \(^{-3}\) results in specific contact resistivity of \(1.7\times 10^{-8}~\Omega \) -cm \(^{2}\) on p+-Ge, which is close to ITRS 15 nm specification (1 \(\times 10^{-8}~\Omega \) -cm \(^{2}\) ) and nearly \(4.5\times \) lower than the state of the art (8 \(\times 10^{-8}~\Omega \) -cm \(^{2}\) ). Cryogenic implantation is shown to enable solid-phase epitaxial regrowth and lower junction depth through amorphization of the surface Ge layer. These improvements in Ge p+/n junctions can pave the way for future high mobility Ge p-MOSFETs. [ABSTRACT FROM AUTHOR]

In this letter, the specific contact resistivity of metal on n-doped germanium is significantly reduced to 3.8\times 10^-7~\Omega\cdot cm^2 by P^+ multiple implantation and multiple annealing (MIMA) technique. The dramatic reduction of specific contact resistivity is attributed to the enhanced activation of n-type dopants, and a high electrical activation over 1\times 10^20~cm^-3 is demonstrated by the spreading resistance profiling analysis. In addition, the fabricated germanium n^+/p diode by P^+ MIMA technique exhibits an ION/IOFF ratio over 10^5 with low ideality factor of 1.11. The low specific contact resistivity of metal on n-doped germanium and well-behaved germanium n^+/p diode are beneficial for the performance improvement of Ge nMOSFETs. [ABSTRACT FROM PUBLISHER]

A \Ge0.976\Sn0.024\ \n^{+}\/p diode was formed using phosphorus ion (\P^+) implant and rapid thermal annealing at 400 ^\circ\C. Activation of P in Ge typically requires high temperatures (e.g., 700 ^\circ \C), and it was found that this is not needed in the presence of a small amount of Sn. A high forward bias current of 320 \A/cm^2 at -1 V is achieved for the \Ge0.976\Sn0.024\ \n^{+}\/p diode. This is four times higher than that of the Ge \n^+\/p control diode, which received the same \P^+ implant but activated at 700 ^\circ\C. The \n^+-GeSn region has a high active dopant concentration of \2.1 \times \10^19\ \cm^-3, much higher than that in the Ge control. The increased active dopant concentration in GeSn reduces the width of the tunneling barrier between the Al contact and the \n^+-GeSn and increases the forward bias diode current. Enhancement of P activation in \Ge0.976\Sn0.024 could possibly be as a result of passivation of vacancies in the Ge lattice due to Sn atoms. [ABSTRACT FROM PUBLISHER]

In this paper we report recent advances in pulsed-laser-deposited AlN thin films for high-temperature capping of SiC, passivation of SiC-based devices, and fabrication of a piezoelectric MEMS/NEMS resonator on Pt-metallized SiO2/Si. The AlN films grown using the reactive laser ablation technique were found to be highly stoichiometric, dense with an optical band gap of 6.2 eV, and with a surface smoothness of less than 1 nm. A low-temperature buffer-layer approach was used to reduce the lattice and thermal mismatch strains. The dependence of the quality of AlN thin films and its characteristics as a function of processing parameters are discussed. Due to high crystallinity, near-perfect stoichiometry, and high packing density, pulsed-laser-deposited AlN thin films show a tendency to withstand high temperatures up to 1600°C, and which enables it to be used as an anneal capping layer for SiC wafers for removing ion-implantation damage and dopant activation. The laser-deposited AlN thin films show conformal coverage on SiC-based devices and exhibit an electrical break-down strength of 1.66 MV/cm up to 350°C when used as an insulator in Ni/AlN/SiC metal-insulator-semiconductor (MIS) devices. Pulsed laser deposition (PLD) AlN films grown on Pt/SiO2/Si (100) substrates for radio-frequency microelectrical and mechanical systems and nanoelectrical and mechanical systems (MEMS and NEMS) demonstrated resonators having high Q values ranging from 8,000 to 17,000 in the frequency range of 2.5-0.45 MHz. AlN thin films were characterized by x-ray diffraction, Rutherford backscattering spectrometry (in normal and oxygen resonance mode), atomic force microscopy, ultraviolet (UV)-visible spectroscopy, and scanning electron microscopy. Applications exploiting characteristics of high bandgap, high bond strength, excellent piezoelectric characteristics, extremely high chemical inertness, high electrical resistivity, high breakdown strength, and high thermal stability of the pulsed-laser-deposited thin films have been discussed in the context of emerging developments of SiC power devices, for high-temperature electronics, and for radio frequency (RF) MEMS. [ABSTRACT FROM AUTHOR]