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A 25.4-33.5 GHz wideband CMOS programmable multi-modulus divider with low power consumption is demonstrated. For a high operating frequency and low power consumption, a direct injection-locked frequency divider is used as the prescaler and followed directly by a dual-modulus divided by 8/9 divider without any driving circuits. The dynamic-loading CML D flip-flips are utilised in the dualmodulus divider which further reduces the power consumption. Implemented in a 90 nm CMOS process, a frequency division from 542 to 654 in steps of 2 is achieved. Measurements show that the self-resonant frequency of the divider is 14.76 GHz, and the locking range is from 25.4 to 33.5 GHz for the total frequency division ratio at an input power of 0 dBm. The power consumption for the maximum division ratio and 0 dBm input power is 15.48 mW at a supply voltage of 1.2 V. The total chip size is 0.72 × 0.47 mm. [ABSTRACT FROM AUTHOR]

A 30-50 GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) with a flat high power gain (S21), along with a flat low-noise figure (NF) is demonstrated for the Atacama large millimetre array (ALMA) band-1 (31.3-45 GHz) system applications. The high S21 and low NF are achieved because the triple-well transistors are utilised with their respective source and body terminals connected together. Furthermore, the bandwidth extension and gain flatness is achieved due to the careful design of the inductive-peaking networks. The LNA has a measured S21 of 21.5 ± 1.5 dB, a minimum NF (NFmin) of 3.8 dB at 32.5 GHz, an average NF (NFavg) of 4.67 dB over the range of 30-50 GHz and an input third-order intercept point (IIP3) of 0 dBm, with a DC power consumption of 20.4 mW at 1.2 V supply. The proposed LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain bandwidth product and highest IIP3 suitable for the ALMA band-1 system applications. [ABSTRACT FROM AUTHOR]