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Summary: A multiplier, as a key component in many different applications, is a time‐consuming, energy‐intensive computation block. Approximate computing is a practical design paradigm that attempts to improve hardware efficacy while keeping computation quality satisfactory. A novel multicolumn 3,3:2 inexact compressor is presented in this paper. It takes three partial products from two adjacent columns each for rapid partial product reduction. The proposed inexact compressor and its derivatives enable us to design a high‐speed approximate multiplier. Then, another ultra‐fast, high‐efficient approximate multiplier is achieved by utilizing a systematic truncation strategy. The proposed multipliers accumulate partial products in only two stages, one fewer stage than other approximate multipliers in the literature. Implementation results by the Synopsys Design Compiler and 45 nm technology node demonstrate nearly 11.11% higher speed for the second proposed design over the fastest existing approximate multiplier. Furthermore, the new approximate multipliers are applied to the image processing application of image sharpening, and their performance in this application is highly satisfactory. It is shown in this paper that the error pattern of an approximate multiplier, in addition to the mean error distance and error rate, has a direct effect on the outcomes of the image processing application. [ABSTRACT FROM AUTHOR]

The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. [ABSTRACT FROM AUTHOR]

Fog computing is considered a formidable next-generation complement to cloud computing. Nowadays, in light of the dramatic rise in the number of IoT devices, several problems have been raised in cloud architectures. By introducing fog computing as a mediate layer between the user devices and the cloud, one can extend cloud computing's processing and storage capability. Offloading can be utilized as a mechanism that transfers computations, data, and energy consumption from the resource-limited user devices to resource-rich fog/cloud layers to achieve an optimal experience in the quality of applications and improve the system performance. This paper provides a systematic and comprehensive study to evaluate fog offloading mechanisms' current and recent works. Each selected paper's pros and cons are explored and analyzed to state and address the present potentialities and issues of offloading mechanisms in a fog environment efficiently. We classify offloading mechanisms in a fog system into four groups, including computation-based, energy-based, storage-based, and hybrid approaches. Furthermore, this paper explores offloading metrics, applied algorithms, and evaluation methods related to the chosen offloading mechanisms in fog systems. Additionally, the open challenges and future trends derived from the reviewed studies are discussed. [ABSTRACT FROM AUTHOR]

Nanomagnetic logic (NML) is a promising candidate for the real implementation of quantum-dot cellular automata circuits and can be a proper alternative or complement to CMOS circuits. Like any other nanoscale technologies, NML circuits are also subject to fabrication variations. These variations along with fluctuations caused by thermal noise can affect the performance of these circuits. Therefore, design of NML circuits with high testability is an absolute necessity. Circuits based on conservative logic are inherently testable because of their specific properties. In this paper, considering the physical and geometrical properties of nanomagnets, a nanomagnetic conservative quantum-dot cellular automata gate is designed and evaluated. This circuit can be used as the basic block for the realization of more complex conservative NML circuits. To implement this circuit, the design of the clocked nanomagnetic majority gate is also provided. The OOMMF physical simulation tool is used for simulation and evaluation. The results show the correct functionality of the proposed conservative gate at room temperature. It operates about 34% faster than the NML Fredkin gate. Moreover, the NML version of the conventional Fredkin gate takes 90% more area than the proposed design. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is a computational paradigm that is based on encoding information in terms of the configuration of charge among quantum dots without requiring current switches. Mostly, QCA cells have been realized by employing the electron switching in square quantum-dot cells. In this paper, a triangular metal-dot cell with a single electron is proposed to represent ternary information. Then, an inverter chain of the proposed triangle cells is suggested through juxtaposing the cells. Additionally, wire crossing and wire fan-out are the two inseparable subjects of QCA wire. A wire-crossing method is presented for the proposed ternary wire. Wire fan-out is also dealt with in this paper by an innovative approach. The correctness of operation of proposed cells and wires are thoroughly verified by applying the physical relations. [ABSTRACT FROM AUTHOR]

Purpose: The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors. Design/methodology/approach: Instead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second proposed designs, respectively. This innovation eliminates threshold detectors from critical path and makes it shorter. Then, the new adders are employed in the image processing application of Laplace filter, which detects edges in an image. Findings: Simulation results demonstrate very high-speed operation for the first and second proposed designs, which are, respectively, 44.7 per cent and 21.6 per cent faster than the next high-speed adder cell. In addition, they make a reasonable compromise between power-delay product (PDP) and other important evaluating factors in the context of approximate computing. They have very few transistors and very low total error distance. In addition, they do not propagate error to higher bit positions by generating output carry correctly. According to the investigations, up to four inexact FA can be used in the Laplace filter computations without a significant image quality loss. The employment of the first and second proposed designs results in 42.4 per cent and 32.2 per cent PDP reduction compared to when no approximate FA are used in an 8-bit ripple adder. Originality/value: Two new current-mode inexact FA are presented. They use diodes as voltage regulators to design current-mode approximate full-adders with very short critical path for the first time. [ABSTRACT FROM AUTHOR]

Purpose: Owing to recent challenges of CMOS manufacturing and power consumption in silicon technologies among alternative technologies, Nanomagnetic logic (NML) is one of the most promising technologies, so it was selected for this study. NML is non-volatile with ultra-low power dissipation that operates at room temperature. This paper aims to propose novel implementation of 2% and 4% multiplexers (MUXs) in NML technology. Design/methodology/approach: The proposed multiplexers in NML technology are verified by HDL-based simulators. In addition, this study estimated area and power dissipation of the proposed design to compare and approve the promising improvements in comparison to other similar NML implementations. Findings: The results show the remarkable improvements in terms of APDP term in comparison to the recent proposed MUXs in NML technology which are reported in Table 2. The proposed implementation of the MUX in NML is designed in three-dimensional layout to improve interconnection complexity which is an integration challenge. Also, by facilitating the routing signals and total wire length needed for clock signals, the negative impact of the power dissipated in clock wires is improved. Originality/value: These findings would appeal to a broad audience, such as the readership of Microelectronics International Journal. The authors confirm that this work is original and has not been published elsewhere nor is it currently under consideration for publication elsewhere. All authors have approved the paper and agreed with submission to Microelectronics International Journal. The authors have read and have abided by the statement of ethical standards for manuscripts submitted to Microelectronics International Journal. The authors have no conflict of interest to declare. [ABSTRACT FROM AUTHOR]

Nanomagnetic logic (NML) has recently been proposed as an attractive and promising implementation of QCA and also as a possible alternative to the CMOS technology. With this emerging technology, it is possible to process and store binary information according to the magnetization state of nanomagnets. Similar to other nanotechnologies, NML circuits are also sensitive to fabrication variations and thermal fluctuations. Therefore, it is highly consequential to improve the testability of these circuits. Circuits based on conservative logic inherently enhance test performance. In this paper, the Fredkin gate, which is one of the most famous conservative reversible gates has been designed and simulated in NML by considering the physical properties of nanomagnets. It can be used to design other testable and ultra-low-power NML circuits as well. OOMMF physical simulation tool is used to simulate and validate the proposed gate at room temperature. The results indicate the correct functionality of the design. [ABSTRACT FROM AUTHOR]

Multiple-valued logic (MVL) can lead to fewer interconnections inside and outside a chip. It can also increase computational performance. Despite these intrinsic advantages, MVL circuits are more prone to noise than the binary counterparts. Since the voltage range is divided into some narrow zones, it is essential to consider noise margins carefully when designing MVL circuits in order to make certain of their suitability and adequate reliability. Several ternary and quaternary inverters, whose voltage transfer characteristics (VTC) suffer from reduced noise margins, have been presented in the literature. This shows that further clarification is definitely required. In this paper, the correct VTC curve of a ternary inverter with proper attributes is clarified. The explanations go beyond ternary logic to cover quaternary and other MVL systems as well. Then, the paper undertakes a review of noise margin and static noise margin measurements for some well-known ternary and quaternary inverters. Besides, the effects of process variation on noise margin are studied. [ABSTRACT FROM AUTHOR]

In recent decades, complementary metal–oxide–semiconductor (CMOS) downscaling has faced some serious challenges such as undesired leakage current densities and high power dissipation. One of the most attractive and promising alternative technologies to CMOS is nanomagnetic logic (NML), which is based on nonvolatile ferromagnetic computing states. In this paper, a novel full adder cell is suggested by providing a feedback loop to a special multilayer nanomagnetic majority voter, which switches between three- and five-input majorities periodically. This solution also represents an example revealing the potential of NML for circuit designs that are not accessible using other technologies such as CMOS or quantum-dot cellular automata (QCA). This capability comes from the combination of a clocking system and the nonvolatile behavior of NML. The correct operation of the new full adder cell is verified using the MQCA Verilog library. Comparisons with other state-of-the-art full adders show significant improvements in terms of density and simplicity. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) circuits are not based on transistors. Therefore, novel concepts and methodologies are required to be able to design Boolean functions in a systematic manner. Wire crossing is a problematic challenge in this technology, imposing considerable cost, complexity, and noise sensitivity. On the other hand, QCA circuits with multiple successive majority gates experience long delays. This paper deals with both problems. At first, some new diagrams are presented for the 13 standard functions, which are sufficient to represent all of the three-input Boolean functions. Some of the standard functions are designed with much fewer wire crossings in this paper compared with the previous designs. Then, with the aim of reducing delay, hierarchical multiplexers are merged together in order to generate wide Boolean functions with fewer layers of majority gates. Circuit compactness is based on some new merging rules. [ABSTRACT FROM AUTHOR]

This paper presents two new 4:2 compressors based on capacitive multi-threshold threshold logic (MTTG), and Carbon Nanotube Field Effect Transistors (CNFETs). The entire capacitor network is divided into two groups in one of the proposed designs. As a result, the number of voltage levels is reduced and the entire structure becomes less sensitive to Process, Voltage, and Temperature variations in comparison with other similar capacitive Threshold Logic (TL) circuits. All designs are simulated by Synopsys HSPICE and 32 nm CNFET technology in different situations and conditions. Simulation results demonstrate the superiority of the second proposed design. It operates 55.9% faster and consumes about 7.2% less power than the second best TL structure (CSTFA). It also operates 16.2% faster and consumes 13.6% less energy in comparison with a traditional design (BLG). Moreover, estimations show that the first proposed design occupies the least area among the capacitive TL circuits. [ABSTRACT FROM AUTHOR]

This study presents a new scalable mathematical approach for designing compressors with any arbitrary number of inputs using multi‐input threshold gates, behaving as exclusive‐OR (XOR). This study relates the theoretical concept to hardware implementation. The methodology is exploited for 3:2, 7:3, and 15:4 compressors, and then implemented by using input capacitors (or resistors) and threshold detectors. The transistor‐level realisation of 3:2 and 7:3 compressors is simulated by using Synopsys HSPICE and 32 nm Carbon Nanotube Field Effect Transistors technology. The proposed methodology benefits from the parallel operation of threshold detectors. Therefore, by increasing the number of inputs, the delay parameter does not increase dramatically. The layout views are also provided in order to be able to compare area for the 3:2 compressors with both capacitor and resistor networks. [ABSTRACT FROM AUTHOR]

This paper deals with the bridge-style circuits. They are highly efficient in terms of transistor density per unit of area. They comply with the conventional CMOS style and form a full-swing and robust structure. First, we clarify the necessary conditions under which a Boolean function can be implemented fully symmetrical. Then, it is demonstrated that it is possible to design out of functions fully symmetrical. Eventually, we show how the pull-up and pull-down networks are constructed in a bridge circuit for any three-input function which fulfils the conditions of being implemented fully symmetrical. [ABSTRACT FROM AUTHOR]

In this paper, a new voltage mirror circuit by using carbon nanotubes (CNTs) technology is presented. This circuit is specifically proposed for the application of duplicating multiple‐valued and fuzzy dynamic random access memories. The given structure prevents any voltage drop for the capacitor inside the memory cell. As a result, any fanout circuit can be driven. The new structure can be utilised for different multiple‐valued logic systems without a change. The unique characteristics of carbon nanotube field effect transistor (CNFET) technology are exploited in this paper to meet the desired design goals. It demonstrates the potentials of CNFET technology in a realistic very large‐scale integration application. The proposed design is highly tolerant to DCNT variation and it is also immune to misaligned CNTs. Simulation results demonstrate that it provides sufficient driving capability with reasonable accuracy. [ABSTRACT FROM AUTHOR]

Novel designs of current-mode Ternary minimum (AND) and maximum (OR) are proposed in this paper based on Carbon NanoTube Field Effect Transistors (CNTFET). First, these Ternary operators are designed separately. Then, they are combined together in order to generate both outputs concurrently in an integrated design. This integration results in the elimination of common parts when both functions are required at the same time. The third proposed current-mode integrated circuit generates both ternary operators with the usage of only 30 transistors. The new designs are composed of three main parts: (1) the part which converts current to voltage; (2) threshold detectors; and (3) the parallel paths through which the output current flows. Unlike the previously presented structure, there is no need for any constant current source within the new designs. This elimination leads to less static power dissipation. The second proposed current-mode segregated Ternary minimum operates 43% faster and consumes 40% less power in comparison with a previously presented structure. [ABSTRACT FROM AUTHOR]