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A classic challenge in chemical sensing is selectivity. Metal–organic frameworks (MOFs) are an exciting class of materials because they can be tuned for selective chemical adsorption. Adsorption events trigger work‐function shifts, which can be detected with a chemical‐sensitive field‐effect transistor (power ≈microwatts). In this work, several case studies were used towards generalizing the sensing mechanism, ultimately towards our metal‐centric hypothesis. HKUST‐1 was used as a proof‐of‐principle humidity sensor. The response is thickness independent, meaning the response is surface localized. ZIF‐8 is demonstrated to be an NO2‐sensing material, and the response is dominated by adsorption at metal sites. Finally, MFM‐300(In) shows how standard hard–soft acid–base theory can be used to qualitatively predict sensor responses. This paper sets the groundwork for using the tunability of metal–organic frameworks for chemical sensing with distributed, scalable devices. [ABSTRACT FROM AUTHOR]

Perspiration-based wearable biosensors facilitate continuous monitoring of individuals' health states with real-time and molecular-level insight. The inherent inaccessibility of sweat in sedentary individuals in large volume (≥10 µL) for on-demand and in situ analysis has limited our ability to capitalize on this noninvasive and rich source of information. A wearable and miniaturized iontophoresis interface is an excellent solution to overcome this barrier. The iontophoresis process involves delivery of stimulating agonists to the sweat glands with the aid of an electrical current. The challenge remains in devising an iontophoresis interface that can extract sufficient amount of sweat for robust sensing, without electrode corrosion and burning/causing discomfort in subjects. Here, we overcame this challenge through realizing an electrochemically enhanced iontophoresis interface, integrated in a wearable sweat analysis platform. This interface can be programmed to induce sweat with various secretion profiles for real-time analysis, a capability which can be exploited to advance our knowledge of the sweat gland physiology and the secretion process. To demonstrate the clinical value of our platform, human subject studies were performed in the context of the cystic fibrosis diagnosis and preliminary investigation of the blood/sweat glucose correlation. With our platform, we detected the elevated sweat electrolyte content of cystic fibrosis patients compared with that of healthy control subjects. Furthermore, our results indicate that oral glucose consumption in the fasting state is followed by increased glucose levels in both sweat and blood. Our solution opens the possibility for a broad range of noninvasive diagnostic and general population health monitoring applications. [ABSTRACT FROM AUTHOR]

We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOx) high- $\kappa $ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide–semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5–5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications. [ABSTRACT FROM PUBLISHER]

In today's digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical "through silicon" micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high- κ/metal gate stacks. [ABSTRACT FROM AUTHOR]

By integrating 3-D nonplanar fins and 2-D ultrathin bodies, wavy FinFETs merge two formerly competing technologies on a silicon-on-insulator platform to deliver enhanced transistor performance compared with conventional trigate FinFETs with unprecedented levels of chip-area efficiency. This makes it suitable for ultralarge-scale integration high-performance logic at and beyond the 10-nm technology node. [ABSTRACT FROM PUBLISHER]

Increased output current while maintaining low power consumption in thin-film transistors (TFTs) is essential for future generation large-area high-resolution displays. Here, we show wavy channel (WC) architecture in TFT that allows the expansion of the transistor width in the direction perpendicular to the substrate through integrating continuous fin features on the underlying substrate. This architecture enables expanding the TFT width without consuming any additional chip area, thus enabling increased performance while maintaining the real estate integrity. The experimental WCTFTs show a linear increase in output current as a function of number of fins per device resulting in \(3.5\times \) increase in output current when compared with planar counterparts that consume the same chip area. The new architecture also allows tuning the threshold voltage as a function of the number of fin features included in the device, as threshold voltage linearly decreased from 6.8 V for planar device to 2.6 V for WC devices with 32 fins. This makes the new architecture more power efficient as lower operation voltages could be used for WC devices compared with planar counterparts. It was also found that field effect mobility linearly increases with the number of fins included in the device, showing almost \(1.8\times \) enhancements in the field effect mobility than that of the planar counterparts. This can be attributed to higher electric field in the channel due to the fin architecture and threshold voltage shift. [ABSTRACT FROM PUBLISHER]

We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high-κ/metal gate based multi-gate-field-effect-transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

We demonstrate a simple, low-cost, and scalable process for obtaining uniform, smooth surfaced, high quality mono-crystalline germanium (100) thin films on silicon (100). The germanium thin films were deposited on a silicon substrate using plasma-assisted sputtering based physical vapor deposition. They were crystallized by annealing at various temperatures ranging from 700 °C to 1100 °C. We report that the best quality germanium thin films are obtained above the melting point of germanium (937 °C), thus offering a method for in-situ Czochralski process. We show well-behaved high- κ /metal gate metal-oxide-semiconductor capacitors (MOSCAPs) using this film. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. [ABSTRACT FROM AUTHOR]

Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in 'ON' state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. Numerical simulations has shown that a 10 nm thin nanotube TFET with a 100 nm core gate has a 5×normalized output current compared to a 10 nm diameter GAA NW TFET. [ABSTRACT FROM AUTHOR]

A low‐cost simple thin film deposition of tin (Sn), followed by thermal annealing based alloying of it into the silicon channel, leads to an enhancement of the performance of silicon‐based CMOS devices. Modelling based on density functional theory (DFT) shows that Sn incorporation may lower the band gap of the silicon channel, while the experimental multi‐gate field effect transistor devices show performance enhancement. Additionally, the device performance analysis indicates its promising usage in low standby power applications for ultra‐mobile computation. The study by Aftab M. Hussain et al. (pp. 332–335) opens up further exploration opportunity for group IV(a) (in the periodic table) based materials for channel engineering in semiconductor device technology. [ABSTRACT FROM AUTHOR]