Search

Negative differential resistance (NDR) devices are adequate candidates for the functional devices applicable to the next‐generation integrated circuit technology so‐called "Beyond CMOS." Here, a graphene velocity‐modulation‐barrier resonant‐tunneling diode operating at room temperature is proposed. The current–voltage characteristics of the device are analyzed using the non‐equilibrium Green's function technique. It is found that the Fermi velocity barrier in the well/barrier region manipulates the tunneling transmission probability by suppressing the Klein region and improving the resonant tunneling leading to NDR. For special values of velocity barriers, resonant states have maximum alignment with each other which increases peak current with a high peak to valley ratio (PVR). The width and the position of the NDR window are controlled and engineered by the device dimensions and the height of potential barriers. The smaller the device showed the better the NDR properties such as larger current density and maximum PVR. Taken together, the results reveal that adequate magnitude of the Fermi velocity in graphene barrier can be an impressive concept for the fabrication of emerging tunneling devices. [ABSTRACT FROM AUTHOR]

A new compact modeling approach is presented which describes the full current-voltage (I-V) characteristic of high-performance (aggressively scaled-down) tunneling field-effect-transistors (TFETs) based on homojunction direct-bandgap semiconductors. The model is based on an analytic description of two key features, which capture the main physical phenomena related to TFETs: (1) the potential profile from source to channel and (2) the elliptic curvature of the complex bands in the bandgap region. It is proposed to use 1D Poisson's equations in the source and the channel to describe the potential profile in homojunction TFETs. This allows to quantify the impact of source/drain doping on device performance, an aspect usually ignored in TFET modeling but highly relevant in ultra-scaled devices. The compact model is validated by comparison with state-of-the-art quantum transport simulations using a 3D full band atomistic approach based on non-equilibrium Green's functions. It is shown that the model reproduces with good accuracy the data obtained from the simulations in all regions of operation: the on/off states and the n/p branches of conduction. This approach allows calculation of energy-dependent band-to-band tunneling currents in TFETs, a feature that allows gaining deep insights into the underlying device physics. The simplicity and accuracy of the approach provide a powerful tool to explore in a quantitatively manner how a wide variety of parameters (material-, size-, and/or geometry-dependent) impact the TFET performance under any bias conditions. The proposed model presents thus a practical complement to computationally expensive simulations such as the 3D NEGF approach. [ABSTRACT FROM AUTHOR]

Triple heterojunction (THJ) tunneling field-effect transistors (TFETs) have been proposed to resolve the low ON-current challenge of TFETs. However, the design space for THJ-TFETs is limited by fabrication challenges with respect to device dimensions and material interfaces. This work shows that the original THJ-TFET design with 12-nm body thickness has poor performance because its subthreshold swing (SS) is 50 mV/decade and the ON-current is only 6 μA/μm. To improve the performance, the doping profile of THJ-TFET is engineered to boost the resonant tunneling efficiency. The proposed THJ-TFET design shows an SS of 40 mV/decade over four orders of drain current and an ON-current of 325 μA/μm with VGS = 0.3 V. Since THJ-TFETs have multiple quantum wells and material interfaces in the tunneling junction, quantum transport simulations in such devices are complicated. State-of-the-art mode-space quantum transport simulation, including the effect of thermalization and scattering, is employed in this work to optimize THJ-TFET design. [ABSTRACT FROM AUTHOR]

The triple heterojunction tunnel field-effect transistor (TFET) has been originally proposed to resolve the TFET’s low ON-current challenge. The carrier transport in such devices is complicated due to the presence of quantum wells and strong scattering. Hence, the full-band atomistic nonequilibrium Green’s function (NEGF) approach, including scattering, is required to model the carrier transport accurately. However, such simulations for devices with realistic dimensions are computationally unfeasible. To mitigate this issue, we have employed the empirical tight-binding mode-space approximation to simulate the triple heterojunction TFETs with the body thickness up to 12 nm. The triple heterojunction TFET design is optimized using the model to achieve a sub-60-mV/decade transfer characteristic under realistic scattering conditions. [ABSTRACT FROM AUTHOR]

The intrinsic limit on ballisticity of ultra-scaled transistors is investigated. A novel probing technique is presented, which locally resolves the loss of incident fluxes. This projection reveals the scalable and unscalable components of reflection. The poor ballisticity is explained by non-equilibrium distribution around the potential barrier, which triggers a substantial unscalable reflections. [ABSTRACT FROM AUTHOR]

Being fundamentally limited to a current–voltage steepness of 60mV/dec, MOSFETs struggle to operate below 0.6 V. Further reduction in ${V}_{\text {DD}}$ and, consequently, power consumption can be achieved with novel devices, such as tunneling transistors (TFETs) that can overcome this limitation. TFETs, however, face challenges with low ON-current leading to slow performance. TFETs made from III-nitride heterostructures are quite promising in this regard. The lattice mismatch induces a piezoelectric polarization field in a nitride heterojunction that can boost the ON-current. However, it is shown here that the carrier thermalization at the heterointerface degrades the subthreshold characteristics. Therefore, a good design should minimize the number of confined quantum well (QW) states at the heterointerface so as not to degrade the subthreshold characteristics while maintaining the lattice mismatch induced polarization to boost the ON-current. We show here that an InAlN QW on an InGaN substrate alloy engineered TFET design is promising to fulfill these requirements. Proper engineering of the alloy mole fractions and the width of the well can eliminate (or at least minimize) the undesired thermalization effects and, at the same time, provide a lattice mismatch to induce a piezoelectric field for boosting the ON-current. We have used a suitable atomistic quantum transport model to simulate these devices. The model accounts for the different mechanisms that are involved, and captures realistic scattering thermalization effects. This model has been benchmarked in our earlier work with experimental measurements of nitride tunneling heterojunction diodes and is used here to optimize the alloy engineered nitride TFET. [ABSTRACT FROM AUTHOR]

The 2-D material-based TFETs are among the most promising candidates for low-power electronics applications since they offer ultimate gate control and high-current drives that are achievable through small tunneling distances ($\Lambda $) during the device operation. The ideal device is characterized by a minimized $\Lambda $. However, devices with the thinnest possible body do not necessarily provide the best performance. For example, reducing the channel thickness (${T}_{\text {ch}}$) increases the depletion width in the source, which can be a significant part of the total $\Lambda $. Hence, it is important to determine the optimum ${T}_{\text {ch}}$ for each channel material individually. In this paper, we study the optimum ${T}_{\text {ch}}$ for three channel materials: WSe2, black phosphorus, and InAs using full-band self-consistent quantum transport simulations. To identify the ideal ${T}_{\text {ch}}$ for each material at a specific doping density, a new analytic model is proposed and benchmarked against the numerical simulations. [ABSTRACT FROM AUTHOR]

In this brief, vertical tunnel field-effect transistors (v-TFETs) based on vertically stacked heretojunctions from 2-D transition metal dichalcogenide materials are studied by atomistic quantum transport simulations. The switching mechanism of a v-TFET is found to be different from previous predictions. As a consequence of this switching mechanism, the extension region where the materials are not stacked over is found to be critical for turning off the v-TFET. This extension region makes the scaling of v-TFETs challenging. In addition, due to the presence of both positive and negative charges inside the channel, v-TFETs also exhibit negative top gate capacitance. As a result, v-TFETs have good energy-delay products and are one of the promising candidates for low-power applications. [ABSTRACT FROM AUTHOR]

Low-dimensional material systems provide a unique set of properties useful for solid-state devices. The building block of these devices is the p-n junction. In this paper, we present a dramatic difference in the electrostatics of p-n junctions in lower dimensional systems, as against the well understood three dimensional (3-D) systems. Reducing the dimensionality increases the depletion width significantly. We propose a novel method to derive analytic equations in 2-D and 1-D that considers the impact of neutral regions. The analytical results show an excellent match with both the experimental measurements and numerical simulations. The square root dependence of the depletion width on the ratio of dielectric constant and doping in 3-D changes to a linear and exponential dependence for 2-D and 1-D, respectively. This higher sensitivity of 1-D p-n junctions to its control parameters can be used toward new sensors. Utilizing the unconventional electrostatics of these low-dimensional junctions for sensing and switching applications has been discussed and a novel sensor is proposed. [ABSTRACT FROM PUBLISHER]

Universality of short-channel effects on saturation current of MOSFETs has been demonstrated. The modulations of carrier injection and transmission rate have been integrated into universal functions. The proposed form has been verified by a large set of quantum transport simulations, where relevant ranges of channel thickness, gate length, and scattering mechanisms are covered. As an application, nonlinear current scaling by channel width is presented for ultrascaled devices. [ABSTRACT FROM PUBLISHER]

Tunneling heterojunctions (THJs) have confined states close to the tunneling region, which significantly affect their transport properties. Accurate numerical modeling of THJs requires combining the nonequilibrium coherent quantum transport through the tunneling region as well as the quasi-equilibrium statistics arising from the strong scattering in the confined states. In this paper, a novel atomistic model is proposed to include both the effects: the strong scattering in the regions around THJ and the coherent tunneling. The new model matches reasonably well with experimental measurements of Nitride THJ and provides an efficient engineering tool for performance prediction and design of THJ-based devices. [ABSTRACT FROM PUBLISHER]

A high performance triple-heterojunction (3HJ) design has been previously proposed for tunneling FETs (TFETs). Compared with single HJ TFETs, the 3HJ TFETs have both shorter tunneling distance and two transmission resonances that significantly improve the ON-state current ( I\scriptscriptstyle {\text {ON}} ). Coherent quantum transport simulation predicts that I\scriptscriptstyle {\text {ON}} = 460~\mu \textsf {A}/\mu \textsf {m} can be achieved at gate length \text Lg = 15~\textsf nm , supply voltage V\textsf {DD} = 0.3~\textsf V , and OFF-state current I\scriptscriptstyle {\text {OFF}} = 1~\textsf {nA}/\mu \textsf {m} . However, strong electron–phonon and electron–electron scattering in the heavily doped leads implies that the 3HJ devices operate far from the ideal coherent limit. In this paper, such scattering effects are assessed by a newly developed multiscale transport model, which combines the ballistic nonequilibrium Green’s function method for the channel and the drift-diffusion scattering method for the leads. Simulation results show that the thermalizing scattering in the leads both degrades the 3HJ TFET’s subthreshold swing through scattering-induced leakage and reduces the turn-ON current through the access resistance. Assuming bulk scattering rates and carrier mobilities, the I\scriptscriptstyle {\text {ON}} is dropped from 460~\mu \textsf A/\mu \textsf m down to 254~\mu \textsf A/\mu \textsf m , which is still much larger than the single HJ TFET case. [ABSTRACT FROM AUTHOR]

Thickness engineered tunneling field-effect transistors (TE-TFET) as a high-performance ultra-scaled steep transistor is proposed. This device exploits a specific property of 2-D materials: layer thickness-dependent energy bandgaps ( Eg ). Unlike the conventional hetero-junction TFETs, TE-TFET uses spatially varying layer thickness to form a hetero-junction. This offers advantages by avoiding the lattice mismatch problems at the interface. Furthermore, it boosts the ON-current to $1280~\mu A/\mu m$ with 15-nm channel length. Providing higher ON currents, phosphorene TE-TFET outperforms the homojunction phosphorene and the TMD TFETs in terms of extrinsic energy-delay product. TE-TFET also scales well to 9 nm with constant field scaling E = V_{DD}/L_{ch}= 33 mV/nm. In this letter, the operation principles of TE-TFET and its performance sensitivity to the design parameters are investigated through full-band atomistic quantum transport simulations. [ABSTRACT FROM PUBLISHER]

A widely used technique to mitigate gate leakage in ultrascaled metal oxide semiconductor field effect transistors ( mosfets) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as \rm SiO_2, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this paper, the effects of high-k oxides on double-gate (DG) mosfet with gate length under 20 nm are studied. All the devices are modeled using an effective mass quantum transport approach based on the quantum transmitting boundary method, where only ballistic transport is considered. We find that there is an optimum physical oxide thickness (\rm T_{OX} ) to achieve the best performance in terms of on-current for each gate stack, including \rm SiO_2 interface layer and one high-k material. For the same EOT, \rm Al_2O_3 (k = 9) over 3-\mathring{\mathrm{A}} \rm SiO_2$ provides the best performance, while for \rm HfO_2$ (k = 22) and \rm La_2O_3$ (k = 30), \rm SiO_2 and 7 \mathring{\mathrm{A}}, respectively. The effects of using high-k oxides and gate stacks on the performance of ultrascaled mosfets are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance. [ABSTRACT FROM PUBLISHER]

In this paper, an analytic model is proposed, which provides, in a continuous manner, the current–voltage ( $I$ – $V$ ) characteristic of high-performance tunneling FETs (TFETs) based on direct bandgap semiconductors. The model provides the closed-form expressions for $I$ – $V$ based on: 1) a modified version of the well-known Fowler–Nordheim (FN) formula (in the ON-state) and 2) an equation that describes the OFF-state performance while providing continuity at the ON/OFF threshold by means of a term introduced as the continuity factor. It is shown that the traditional approaches, such as FN, are accurate in TFETs only through correct evaluation of the total band bending distance and the tunneling effective mass. General expressions for these two key parameters are provided. Moreover, it is demonstrated that the tunneling effective mass captures both the ellipticity of evanescent states and the dual (electron/hole) behavior of the tunneling carriers, and it is further shown that such a concept is even applicable to semiconductors with nontrivial energy dispersion. Ultimately, it is found that the $I$ – $V$ characteristics obtained by using this model are in close agreement with the state-of-the-art quantum transport simulations both in the ON- and OFF-state, thus providing the validation of the analytic approach. [ABSTRACT FROM PUBLISHER]

Self-assembled quantum dots (QDs) are highly strained heterostructures. The lattice strain significantly modifies the electronic and optical properties of these devices. A universal behavior is observed in atomistic strain simulations (in terms of both strain magnitude and profile) of QDs with different shapes and materials. In this paper, this universal behavior is investigated by atomistic as well as analytic continuum models. Atomistic strain simulations are very accurate but computationally expensive. On the other hand, analytic continuum solutions are based on assumptions that significantly reduce the accuracy of the strain calculations, but are very fast. Both techniques indicate that the strain depends on the aspect ratio (AR) of the QDs, and not on the individual dimensions. Thus, simple closed-form equations are introduced which directly provide the atomistic strain values inside the QD as a function of the AR and the material parameters. Moreover, the conduction and valence band edges EC/V and their effective masses m^*C/V of the QDs are dictated by the strain and AR consequently. The universal dependence of atomistic strain on the AR is useful in many ways. Not only does it reduce the computational cost of atomistic simulations significantly, but it also provides information about the optical transitions of QDs given the knowledge of EC/V and m^*C/V from AR. Finally, these expressions are used to calculate optical transition wavelengths in InAs/GaAs QDs, and the results agree well with the experimental measurements and atomistic simulations. [ABSTRACT FROM AUTHOR]

The main promise of tunnel FETs (TFETs) is to enable supply voltage ( V\mathrm{ DD} ) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing V\mathrm{ DD} and channel length ( L\mathrm{ ch} ) typically deteriorates the ON- and OFF-state performance of TFETs, respectively. Accordingly, there is not yet any report of a high-performance TFET with both low V\mathrm{ DD} ( \sim 0.2 V) and small L\mathrm{ ch} ( \sim 6 nm). In this letter, it is shown that scaling TFETs in general requires scaling down the bandgap Eg and scaling up the effective mass m^{*} for high performance. Quantitatively, a channel material with an optimized bandgap ( Eg\sim 1.2qV\mathrm{ DD} [eV]) and an engineered effective mass ( m^*^-1\sim 40 V\mathrm{ DD}^{2.5} [{\mathrm{ m}}0^-1] ) makes both V\mathrm{ DD} and L\mathrm{ ch} scaling feasible with the scaling rule of L\mathrm{ ch}/V\mathrm{ DD}=30 nm/V for L\mathrm{ ch} from 15 to 6 nm and the corresponding V\mathrm{ DD} from 0.5 to 0.2 V. [ABSTRACT FROM PUBLISHER]

The dielectric engineered tunnel field-effect transistor (DE-TFET) as a high-performance steep transistor is proposed. In this device, a combination of high- $k$ and low- k$ dielectrics results in a high electric field at the tunnel junction. As a result, a record ON-current of \sim 1000~\mu \text{A}/\mu \text{m} and a subthreshold swing (SS) below 20 mV/decade are predicted for WTe2 DE-TFET. The proposed TFET works based on a homojunction channel and electrically doped contacts both of which are immune to interface states, dopant fluctuations, and dopant states in the bandgap, which typically deteriorate the OFF-state performance and SS in the conventional TFETs. [ABSTRACT FROM PUBLISHER]

Nanoelectronic transistors have reached 3D length scales in which the number of atoms is countable. Truly atomistic device representations are needed to capture the essential functionalities of the devices. Atomistic quantum transport simulations of realistically extended devices are, however, computationally very demanding. The widely used mode space (MS) approach can significantly reduce the numerical cost, but a good MS basis is usually very hard to obtain for atomistic full-band models. In this work, a robust and parallel algorithm is developed to optimize the MS basis for atomistic nanowires. This enables engineering-level, reliable tight binding non-equilibrium Green's function simulation of nanowire metal-oxide-semiconductor field-effect transistor (MOSFET) with a realistic cross section of 10 nm × 10 nm using a small computer cluster. This approach is applied to compare the performance of InGaAs and Si nanowire n-type MOSFETs (nMOSFETs) with various channel lengths and cross sections. Simulation results with full-band accuracy indicate that InGaAs nanowire nMOSFETs have no drive current advantage over their Si counterparts for cross sections up to about 10 nm × 10 nm. [ABSTRACT FROM AUTHOR]

Traditional thinking assumes that a light effective mass ($m^*$ ), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light $m^*$ may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance ($C_q$ ). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum $m^*$ for sub-12-nm nanowire down to channel length of 3 nm. Optimum $m^*$ are found to range between 0.2–1.0 $m_0$ and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. $m^*$ is no longer a material constant, but a geometry and strain dependent property of the channel material. [ABSTRACT FROM PUBLISHER]

In this letter, it is shown that the existing scaling theories for chemically doped transistors cannot be applied to the novel class of electrically doped 2D transistors and the concept of equivalent oxide thickness (EOT) is not applicable anymore. Hence, a novel scaling theory is developed based on analytic solutions of the 2D Poisson equation. Full band atomistic quantum transport simulations verify the theory and show that the critical design parameters are the physical oxide thickness and distance between the gates. Accordingly, the most optimized electrically doped devices are those with the smallest spacing between the gates and the thinnest oxide, and not the smallest EOT. [ABSTRACT FROM AUTHOR]