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This article proposes a two-stage 48-V voltage regulator module using a hybrid switched-capacitor converter in the first stage. Apart from being compact in nature, this first-stage converter has several other advantages such as efficient regulation ability and hence scalability, inherent full/partial soft switching for most of the switches, reduced switch voltage and current stresses, and the possibility of wide range variable switching frequency operation. These combined features together help to obtain a flat high-efficiency curve for the first stage. The second-stage multiphase buck converter also exhibits flat high-efficiency characteristics through phase shedding. Steady-state circuit operation and analysis of the first-stage converter is presented in this article. An accurate discrete-time model of the first-stage converter is also developed. Thereafter, a design guideline for the two-stage converter is discussed. Finally, experimental results from an 80-W laboratory prototype show that the proposed converter possesses a relatively flat high-efficiency profile and exhibits a faster load transient response compared to that of the state-of-the-art solutions. [ABSTRACT FROM AUTHOR]

A buck-derived transformer-isolated converter topology has been proposed in this article for the single-stage 48-V voltage regulator module (VRM) application. The proposed converter uses a switched-capacitor voltage divider derived stacked half-bridge circuit in the primary side of the transformer. This simplifies the transformer structure and reduces device voltage ratings compared to the conventional half-bridge or a full-bridge circuit. Detailed circuit operation, analysis, and design of the proposed converter are presented. Further circuit modification is proposed to avoid unequal average inductor current sharing due to unequal resistances of the inductors in the secondary-side current doubler rectifier and consequent load-dependent dc shift in the transformer magnetizing current. An averaged small-signal ac equivalent circuit model of the converter is derived and validated against SIMPLIS simulation results. Finally, experimental results from a GaN device-based 45-A laboratory prototype demonstrates a maximum efficiency of 92.7%, which is higher than that of the state-of-the-art solution for the selected specifications, and exhibits faster dynamic response against load step variations. [ABSTRACT FROM AUTHOR]

This paper proposes a ripple injection method in a two-stage intermediate bus architecture to overcome the incremental negative-impedance effect in the intermediate bus converter (IBC) induced by the constant power load, which is essentially a tightly regulated point of load (PoL) converter. The proposed method uses the voltage ripple of the intermediate bus in the feedback path for the closed-loop PoL converter while operating the IBC in open loop. The small-signal model is derived and verified using SIMPLIS simulation. The voltage ripple is shown to carry the inductor current information of the PoL converter. Thus, the proposed scheme is expected to retain the superior line regulation of current mode control for the PoL converter even without sensing the inductor current. Load current feed forward can improve the transient response for the PoL converter. Moreover, the load current information is also used to generate the appropriate duty ratio for the IBC during transient recovery. A simple PI controller is used for the PoL converter, which reduces the design complexity using the proposed control scheme. A hardware prototype is made, and the superior performance using the proposed control scheme is experimentally verified. [ABSTRACT FROM AUTHOR]

The right-half-plane (RHP) zero in a continuous conduction mode boost converter results in a significantly restricted closed-loop bandwidth (BW) for higher voltage gain and/or load current conditions. A compensating ramp is used for current-mode control (CMC), and a higher ramp slope degrades the BW. Variable-frequency digital CMC offers inherent current-loop stability and real-time tuning scope for higher closed-loop BW. However, the challenges are to select the sampling frequency and sampling instant of the output voltage with discontinuous ripple due to the effective series resistance of the output capacitor, and its impact on stability. This paper shows that an event-based current-mode constant off-time digital modulator achieves superior stability and performance in a boost converter along with the reduced RHP zero effect over other digital CMC techniques. Using a discrete-time framework, the fast-scale stability conditions and small-signal models are analytically derived for various digital CMC techniques, which are validated using SIMPLIS simulation. A boost converter prototype is tested, and the analytical predictions are verified experimentally. Further, the analysis is extended to a non-inverting buck–boost converter. [ABSTRACT FROM AUTHOR]

The output voltage of a voltage-mode digitally pulse-width-modulated (DPWM) dc–dc converter is sampled once per switching cycle, and past studies show the existence of limit cycle oscillations due to quantization. This brief reports that the map of a continuous conduction mode (CCM) buck converter under DPWM is shown to be discontinuous and exhibits border collision bifurcations mainly because of a sampling delay. The discrete-time state space is piecewise smooth, divided into nine regions with different functional forms and separated by eight boundaries. This is unlikely using analog PWM, in which only three regions and two borders exist under CCM. The closed-form stability conditions are derived and design methods are discussed to enhance the stability boundary. A prototype buck converter is tested. Experimental bifurcation diagrams and time domain results are demonstrated to support the analytical predictions. [ABSTRACT FROM AUTHOR]

Ripple-based constant on-time and off-time control techniques can achieve fast step-down and step-up transient performance along with an improved light-load efficiency. However, they suffer from varying switching frequency at the steady state and often require a phase-locked loop for frequency regulation. This paper proposes a constant on/off-time hybrid modulation technique in a digitally current-mode controlled synchronous buck converter. The proposed technique considers an event-based sampling mechanism using one sample per switching cycle, which makes it useful for high-frequency implementation. This requires a monoshot timer and a digital voltage controller $G_c(z)$. The proposed technique can be configured to a constant on-time or off-time modulator with seamless transition because of sharing $G_c(z)$ ; thus, improved step-up/down transient performance can be retained. Furthermore, a discrete-time framework is proposed for fast-scale stability analysis, and the effects of finite sampling and practical parasitics are discussed. Discrete-time small-signal models are derived for the direct digital control design with enhanced stability and performance. A frequency adaptation method is discussed to customize the switching frequency in real time. A buck converter prototype is tested, and the usefulness of the proposed modulation technique is verified experimentally. [ABSTRACT FROM AUTHOR]

In the recent years, digital current mode control has gained popularity due to its technical benefits. However, designers face difficulties in controller design due to the delays associated with analog-to-digital (A/D) converter and controller computation. In software-based digital controller implementation, the cumulative delay of A/D conversion and controller computation may be comparable to the switching time period. This brief shows that the one-cycle delay in digital implementation in fact enhances the stability margin in a mixed-signal current mode controlled buck converter. By deriving a discrete-time model, we obtain the stability region in the parameter space and show that, if the controller gain is set within a specific range, the software-based implementation can achieve stable periodic (period-1) behavior without a ramp compensation even when the duty ratio exceeds 0.5. The theoretical results are validated with a buck converter prototype with a digital controller realized on an FPGA device. [ABSTRACT FROM AUTHOR]

Digital implementation of current-mode control (CMC) considers the outer voltage-loop in the digital domain, whereas the inner current-loop is kept either in the analogue domain in mixed-signal CMC (MCMC) or in the digital domain in fully digital CMC (DCMC). Under finite voltage-loop sampling, this study reports that the selection of sampling point can completely change the stability status of a boost converter with non-minimum phase behaviour, particularly in the presence of the effective-seriesresistance of the output capacitor. A discrete-time framework is proposed for fast-scale stability analysis in a boost converter, operating under continuous conduction mode. Further, discrete-time small-signal models are derived and design guidelines are proposed for both MCMC and DCMC architectures with enhanced stability for fast transient performance. Keeping in mind software-controlled DCMC, a considerably large sampling delay is considered, and its effect on the performance and stability is discussed. A boost converter prototype is tested and various DCMC schemes along the proposed design techniques are implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

Dynamic voltage scaling (DVS) is a useful technique to optimize performance and efficiency of CMOS digital processors using dc–dc converters that require to meet extremely fast slew rate demand. However, there exist conflicting design criteria in existing DVS power supply architectures. This paper proposes a single-inductor multioutput-level buck converter for low power DVS-enabled systems. Under the time optimal voltage transition recovery, the proposed architecture: first, achieves the performance much beyond system's physical limits compared to conventional synchronous and multiphase buck converter based architectures; and second, can overcome conflicting power circuit design criteria in existing architectures. Also, a high-resolution quantized voltage can be realized by using a voltage-dithering technique. An analytical framework is considered to formulate various processor and converter-induced energy overheads. A comparative study is shown to evaluate the usefulness of the proposed architecture over the existing approaches under frequent voltage transitions. A prototype single-inductor four-output-level buck converter is tested and the performance improvements are demonstrated using test results. [ABSTRACT FROM PUBLISHER]

The inductor current ripple under hysteresis current control is sensitive to system as well as controller parameters, which often deviates from the desired band. Thus, a phase-locked-loop (PLL) is employed to regulate the switching frequency over the operating range. Digital platform drastically simplifies this using an all-digital PLL (ADPLL) and offers the controller-tuning flexibility for improved performance. However, the use of uniform voltage-sampling often leads to multilimit cycle instability. This paper proposes a mixed-signal hysteretic current controller (MSHCC) with the digital voltage-loop and the analog current-loop. A digital-to-analog converter is sufficient to generate time-multiplexed current references. This achieves robust stability and parameter-insensitive current ripple by sampling the error-voltage at the rising edge of the high-side gate signal. Stability analysis is carried out using discrete-time models. The proposed MSHCC can be configured to either of the peak, average, or valley current-mode techniques along with the flexibility to adjust the switching frequency using an ADPLL for real-time energy-optimization. The proposed scheme is implemented using an FPGA device and tested on a buck converter prototype. The MSHCC scheme can be extended to a multiphase buck converter. [ABSTRACT FROM AUTHOR]

Linear small-signal models of a dc–dc converter often ignore switching dynamics; thus such models are insufficient to fully explore the performance objective under large signal transients. Linear/nonlinear hybrid controllers are promising alternatives; however, they require structurally different hardware resources along with extra antiwindup arrangements. This paper proposes a geometric tuning method in a digitally current-mode-controlled buck converter under continuous-conduction mode. This considers a proportional-integral voltage controller along with a load current feedforward in the digital domain, while the inductor current has a traditional analog implementation. This resembles a first-order switching surface with near load-invariant regulation; thus a (fixed) small integral gain is sufficient to minimize the steady-state error. Using phase-plane geometry, the objective is to tune the controller gain in a way to achieve proximate time optimal recovery using a fixed-frequency pulse-width modulator and also to retain the large-signal stability. The effects of parameter variation and finite sampling are analyzed. The proposed tuning is implemented using an FPGA device. [ABSTRACT FROM AUTHOR]

Majority of spectral spreading techniques employ chaos-based pulsewidth-modulation (PWM) schemes in a switching dc–dc converter, in which neither dynamic performance nor ripple parameter can be correctly predicted so as for efficiency. Periodic frequency modulation using a triangular carrier wave can achieve custom spectral spreading and harmonic reduction. This paper proposes a periodic bifrequency digital PWM (BF-DPWM) technique in a dc–dc converter, which uses two discrete frequencies f1 and f2 as guided by a modulating signal fm. Fourier analysis shows that f1 and f2 do not exist; however, they contribute to power spectrum of fm. This method achieves considerable harmonic reduction and improved DPWM resolution with an insignificant ripple impact, compared to a dither-based periodic modulation scheme. Design guidelines using simulation study are presented. A buck converter prototype has been made, and different control schemes are implemented using a field-programmable gate array device. Test results show that the BF-DPWM has insignificant impacts on transient performance. Finally, the proposed scheme is extended to the triangular-wave modulation scheme, which results in further harmonic reduction. [ABSTRACT FROM PUBLISHER]

A pulse skipping modulation (PSM) technique improves the light load efficiency in a dc–dc converter by selectively skipping a few clock pulses. However, in existing PSM schemes, the number of charge and/or skipped cycles cannot be predefined. Therefore, it is difficult to predict the ripple parameters and ensure a stable periodic behavior. Further, it becomes difficult to further minimize power losses under light load conditions. This paper proposes a voltage-mode digital pulse skipping modulator which uses a digital pulse-width-modulator (PWM) as a building block, thus making it easy to operate the system in both PWM and PSM modes. Unlike in existing PSM schemes, the sequence and the count of charge and skip cycles can be fully prespecified in the proposed scheme, with the number of skip cycles optimally chosen to maximize the efficiency. Stability analysis is carried out using discrete-time modeling, which provides guidelines to ensure a stable periodic operation with predictable ripple parameters. Small-signal modeling and design of the proposed PSM scheme are discussed. A prototype buck converter was fabricated and tested. The proposed control scheme is implemented using an FPGA device, and the experimental results fully support the analytical predictions. [ABSTRACT FROM PUBLISHER]

Efficiency in a light load dc–dc converter is improved by reducing the switching frequency with the load current. Further, a bifrequency operation (BFO) using pulse train (PT) control can achieve spread spectrum. Using discrete-time models, this paper shows that a stable periodic BFO is generally not achievable in existing PT control methods. Thereafter, a unified multimode digital control technique is proposed, in which a voltage-mode digital pulse-width-modulator (DPWM) is used to control a predefined periodic BFO. Beside the fixed-frequency DPWM, an extra multiplexer is considered for real-time configuration to: 1) bifrequency pulse frequency modulation; 2) PT control; or 3) pulse regulation control; or 4) pulse skipping control with smooth transition. Analysis and design methods are discussed to ensure periodic BFO and to customize the power spectrum with predictable ripple parameters. A buck converter prototype is made, and the proposed control is implemented using an FPGA device. [ABSTRACT FROM PUBLISHER]

Benefits of digital current mode control are often limited by the choice of a current-loop sampling rate. A higher rate requires a fast analog-to-digital converter that consumes substantial power and increases cost. A lower rate often results in subharmonic oscillations, even using a programmable ramp compensation. This brief proposes a simple technique to compute the steady-state duty ratio in real time, when the closed-loop controller is in action. A time-to-digital converter translates cycle-by-cycle duty ratio information into digital code, and a “duty ratio computation” block generates the computed duty ratio using a moving average filter. At steady state, this enforces a virtual open-loop configuration and completely disables current-loop sampling and controller computation, thereby saving substantial power and eliminating subharmonic oscillations. Considering a dc–dc buck converter as the test case, it is found that even in the presence of high periodic behavior under the closed-loop control, a near-ideal steady-state duty ratio can be reconstructed. Design-related issues along with duty ratio saturation are discussed with test cases. [ABSTRACT FROM PUBLISHER]

A pulse skipping modulation (PSM) technique is useful for improving the efficiency of a dc-dc converter under light load conditions. Under such condition, the discrete-time model of the converter could be modeled as a discontinuous map, comprising either 1D functions only or a combination of 1D and 2D functions. Using the PSM mechanism, efficiency and spectral composition could be further improved by incorporating a voltage feedback loop. In this paper we show that, in a converter under voltage controlled PSM, the entire map can be restricted to one dimension for a wide range of parameters, by properly designing the controller. As a parameter is varied, the periodicity of the output waveform may change either monotonically or non-monotonically depending on the character of the voltage mode control loop. Technically it is desirable to operate the converter in such a way that a variation of a parameter can cause only incremental change in the periodicity and hence in the spectral composition. In the nonlinear dynamics literature, such a bifurcation scenario is known as pure period incrementing cascade. Using the theory for 1D discontinuous maps, we obtain the conditions on the converter's parameters such that such a cascade is obtained, and the variation of a parameter does not cause large variation of the periodicity. The results have been experimentally validated. [ABSTRACT FROM AUTHOR]

A novel current mode control scheme for the tristate boost converter circuit is proposed, which eliminates the zero in the right-half plane (RHP), and improves the dynamic performance. The tristate boost converter contains an additional switch across the inductor. Within a clock cycle, the inductor current first rises during the ON interval of the main switch, then falls during the OFF or capacitor charging interval, and finally, remains almost constant during the freewheeling interval when the additional switch is turned on. In the proposed controller, the peak value of the inductor current is controlled by peak current mode control using an outer voltage feedback loop, whereas the freewheeling current is controlled by the input voltage and the reference voltage feedforward path. Applying both feedback as well as feedforward control on the inductor current significantly improves the output voltage regulation, audio susceptibility, and transient responses. We show that the RHP zero is completely eliminated from the closed-loop control-to-output transfer function. This results in a very large bandwidth, and hence a superior dynamic performance. The latter is established by comparison with the voltage-mode- and current-mode-controlled classical boost converters that suffer from the RHP zero problem, as well as with other tristate boost converter control techniques like the constant charging interval and dual mode control, recently proposed in the literature. Significant superiority of the proposed scheme is established both through simulation and experimentation. [ABSTRACT FROM AUTHOR]