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This Letter investigates the cryogenic behavior of NbO2 threshold switching devices. Pt/NbO2/Pt devices are demonstrated to be well functional as threshold switching devices at ultra-low temperature (4 K). When the temperature decreases, the OFF-state resistance of NbO2 increases and the switching voltage increases. With the extracted characteristics of NbO2 ranging from 4 K to 300 K, we continue to study the neuromorphic system using the crossbar array with resistive memories as resistive synapses and NbO2 as oscillation neurons at different temperatures through SPICE simulation. The simulation results show that the oscillation systems could still work properly at 4 K. The oscillation amplitude decreases as temperature increases. The oscillation frequency depends on both the temperature and the input voltage. [ABSTRACT FROM AUTHOR]

A ferroelectric field-effect transistor (FeFET) with scaled dimensions (170 nm and 24 nm of gate width and length, respectively) and a 10 nm thick Si doped HfO 2 ferroelectric in the gate oxide stack are characterized at cryogenic temperatures down to 6.9 K. We observe that a decrease in temperature leads to an increase in the memory window at the expense of an increased program/erase voltage. This is consistent with the increase in the ferroelectric coercive field due to the suppression of thermally activated domain wall creep motion at cryogenic temperatures. However, the observed insensitivity of the location of the memory window with respect to temperature cannot be explained by the current understanding of the device physics of FeFETs. Such temperature dependent studies of scaled FeFETs can lead to useful insights into their underlying device physics, while providing an assessment of the potential of this emerging technology for cryogenic memory applications. [ABSTRACT FROM AUTHOR]

Negative capacitance field-effect transistors (NCFETs) with optimal ferroelectric parameters provide phenomenal power reduction as discussed in Part I. In this part, we explore the impact of operating voltage on power consumption at the device, gate, and full-chip levels. We first observe that high operating voltages applied to NCFET devices lead to an abrupt increase in both the drain current and the gate capacitance. Furthermore, negative capacitance is lost when the voltage is set too high. On the other hand, the gate capacitance increase still exists, although with smaller magnitude, even at low operating voltages. This helps reduce device delay and eventually full-chip delay. Furthermore, delay improvement at the full-chip level can be traded off to gain power reduction at the full-chip level. Finally, our experiments suggest that a sufficiently low supply voltage (= 0.4 V out of [0.2 and 0.8 V] range in our study) is needed to maximize power and performance gain at full-chip level. [ABSTRACT FROM AUTHOR]

In this two-part article, we propose a framework for selecting ferroelectric oxide material for the design of a negative capacitance field-effect transistor (NCFET). The investigation is based on an exhaustive search of two important ferroelectric material parameters: remnant polarization and coercive field in the context of their negative capacitance properties. The effects of these parameters are first studied at the NCFET device level and systematically extended up to the full-chip level. Based on this search, we arrive at the notion of optimality of ferroelectric parameters for a given “isoperformance full-chip benchmark”: The power dissipation in a specific circuit/system is maximally reduced by using optimized NCFETs while meeting the target performance. In Part I, we develop the framework for identifying optimal ferroelectric parameters at a given VDD. This sets the stage for Part II, where we investigate the optimal ferroelectric parameters as VDD is scaled. [ABSTRACT FROM AUTHOR]

As computational models inspired by the biological neural system, spiking neural networks (SNN) continue to demonstrate great potential in the landscape of artificial intelligence, particularly in tasks such as recognition, inference, and learning. While SNN focuses on achieving high-level intelligence of individual creatures, Swarm Intelligence (SI) is another type of bio-inspired models that mimic the collective intelligence of biological swarms, i.e., bird flocks, fish school and ant colonies. SI algorithms provide efficient and practical solutions to many difficult optimization problems through multi-agent metaheuristic search. Bridging these two distinct subfields of artificial intelligence has the potential to harness collective behavior and learning ability of biological systems. In this work, we explore the feasibility of connecting these two models by implementing a generalized SI model on SNN. In the proposed computing paradigm, we use SNNs to represent agents in the swarm and encode problem solutions with the spike firing rate and with spike timing. The coupled neurons communicate and modulate each other's action potentials through event-driven spikes and synchronize their dynamics around the states of optimal solutions. We demonstrate that such an SI-SNN model is capable of efficiently solving optimization problems, such as parameter optimization of continuous functions and a ubiquitous combinatorial optimization problem, namely, the traveling salesman problem with near-optimal solutions. Furthermore, we demonstrate an efficient implementation of such neural dynamics on an emerging hardware platform, namely ferroelectric field-effect transistor (FeFET) based spiking neurons. Such an emerging in-silico neuron is composed of a compact 1T-1FeFET structure with both excitatory and inhibitory inputs. We show that the designed neuromorphic system can serve as an optimization solver with high-performance and high energy-efficiency. [ABSTRACT FROM AUTHOR]

We demonstrate that a ferroelectric field-effect transistor (FeFET)-based spiking neuron is capable of mimicking various spiking and bursting patterns characteristic of cortical neurons. We propose a compact model to describe the dynamical behavior of such FeFET-based spiking neurons. This model captures the current-voltage dynamics of the FeFET and the critical voltages of its hysteretic region. It is aimed at system-level modeling and simulation of biomimetic networks of the FeFET neurons that are ideal for neuromorphic computing. [ABSTRACT FROM AUTHOR]

Negative capacitance is a newly discovered state of ferroelectric materials that holds promise for electronics applications by exploiting a region of thermodynamic space that is normally not accessible1-14. Although existing reports of negative capacitance substantiate the importance of this phenomenon, they have focused on its macroscale manifestation. These manifestations demonstrate possible uses of steady-state negative capacitance—for example, enhancing the capacitance of a ferroelectric-dielectric heterostructure4,7,14 or improving the subthreshold swing of a transistor8-12. Yet they constitute only indirect measurements of the local state of negative capacitance in which the ferroelectric resides. Spatial mapping of this phenomenon would help its understanding at a microscopic scale and also help to achieve optimal design of devices with potential technological applications. Here we demonstrate a direct measurement of steady-state negative capacitance in a ferroelectric-dielectric heterostructure. We use electron microscopy complemented by phase-field and first-principles-based (second-principles) simulations in SrTiO3/PbTiO3 superlattices to directly determine, with atomic resolution, the local regions in the ferroelectric material where a state of negative capacitance is stabilized. Simultaneous vector mapping of atomic displacements (related to a complex pattern in the polarization field), in conjunction with reconstruction of the local electric field, identify the negative capacitance regions as those with higher energy density and larger polarizability: the domain walls where the polarization is suppressed. Imaging steady-state negative capacitance in SrTiO3/PbTiO3 superlattices with atomic resolution provides solid microscale support for this phenomenon. [ABSTRACT FROM AUTHOR]

We demonstrate an electrically induced, non-volatile, metal-insulator phase transition in a MoS2 transistor. A ferroelectric capacitor made of single crystalline, epitaxially grown PbZr0.2Ti0.8O3 was connected to the gate of a field effect thin film MoS2 transistor. When a voltage is applied to this ferroelectric capacitor, a clear transition from an insulator to a metal and vice versa is observed in the transistor. Importantly, when the biased voltage is turned off, the remnant polarization in the ferroelectric can keep the MoS2 in its original phase, thereby providing a non-volatile state. Thus, a metallic or insulating phase can be written, erased, or retained simply by biasing the externally connected ferroelectric capacitor. [ABSTRACT FROM AUTHOR]

We demonstrate that a ferroelectric can cause a differential voltage amplification without needing an external energy source. As the ferroelectric switches from one polarization state to the other, a transfer of energy takes place from the ferroelectric to the dielectric, determined by the ratio of their capacitances, which, in turn, leads to the differential amplification. This amplification is very different in nature from conventional inductor-capacitor based circuits where an oscillatory amplification can be observed. The demonstration of differential voltage amplification from completely passive capacitor elements only has fundamental ramifications for next generation electronics. [ABSTRACT FROM AUTHOR]

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of >10^10 read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated. [ABSTRACT FROM PUBLISHER]

To further reduce the power dissipation in nanoscale transistors, the fundamental limit posed by the Boltzmann distribution of electrons has to be overcome. Stabilization of negative capacitance in a ferroelectric gate insulator can be used to achieve this by boosting the transistor gate voltage. Up to now, negative capacitance is only directly observed in polymer and perovskite ferroelectrics, which are incompatible with semiconductor manufacturing. Recently discovered HfO2-based ferroelectrics, on the other hand, are ideally suited for this application because of their high scalability and semiconductor process compatibility. Here, for the first time, a direct measurement of negative capacitance in polycrystalline HfO2-based thin films is reported. Decreasing voltage with increasing charge transients are observed in 18 and 27 nm thin Gd:HfO2 capacitors in series with an external resistor. Furthermore, a multigrain Landau-Khalatnikov model is developed to successfully simulate this transient behavior in polycrystalline ferroelectrics with nucleation limited switching dynamics. Structural requirements for negative capacitance in such materials are discussed. These results demonstrate that negative capacitance effects are not limited to epitaxial ferroelectrics, thus significantly extending the range of potential applications. [ABSTRACT FROM AUTHOR]

In this Letter, the first name of author Bhagwati Prasad was misspelled Bhagawati. This error has been corrected online. [ABSTRACT FROM AUTHOR]

A correction is presented to the article "Differential voltage amplification from ferroelectric negative capacitance" which was published in the perodical.