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Appearances of specific transition patterns during data transfer in bus lines of modern high-performance computing systems, such as communicating structures of accelerators for deep convolutional neural networks, commercial Network on Chips, and memories, can lead to crosstalk faults. With the shrinkage of technology size, crosstalk faults occurrence boosts and leads to degradation of reliability and performance, as well as the increasing power consumption of lines. One effective way to alleviate crosstalk faults is to avoid the appearance of these specific transition patterns by using numerical-based crosstalk avoidance codes (CACs). However, a serious problem with numerical-based CACs is their overheads in terms of required additional bus lines for representing code words. To solve this problem, in this paper we present a novel CAC that is based on the use of three symbols (three-value) to represent the code words in the bus lines, rather than classical binary CACs based on binary, i.e., 0 and 1 symbols. Our proposed CAC, named summation-based tri-value crosstalk avoidance code (ST-CAC), reduces the worst-case delay in bus lines with respect to binary CACs, and it can efficiently be applied to any arbitrary channel width of lines. The use of three symbols to represent code words in ST-CAC enables to increase the number of code words of a numerical system without increasing the number of required bus lines significantly. The experimental results show that CACs based on the use of three symbols can reduce the number of additional lines compared to binary CACs by 33%. Moreover, we show in the paper, that the delay of wires in the presence our ST-CAC can reduce by 33% with respect to state-of-the-art binary value CACs. [ABSTRACT FROM AUTHOR]

Summary: A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter‐based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n‐channel metal‐oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power benefits of the proposed comparator were verified using analytical derivations, PVT corners, and post layout simulations. The results confirm that the introduced technique reduces the power consumption by 60%, also, provides 57% better comparison speed for an input common mode voltage (Vcm) range of 0‐Vdd/2. [ABSTRACT FROM AUTHOR]

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$. The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz. [ABSTRACT FROM AUTHOR]

A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching procedure and they are verified using MATLAB simulations. Postlayout simulations in 0.18 μm technology and a fabricated PCB using off-the-shelf components prove the analytical derivations and the benefits of the proposed switching procedure. [ABSTRACT FROM PUBLISHER]