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Your search keyword '"Kuo, Ron-Chi"' showing total 5 results
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5 results on '"Kuo, Ron-Chi"'

2. On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers.

Author

Chih-Lin Chen, Hsin-Yuan Tseng, Kuo, Ron-Chi, and Wang, Chua-Chin

Abstract

A novel PVT (Process, Voltage, Temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, voltage, and temperature deviation could be detected, respectively. The proposed design is implemented using a typical 90 nm CMOS process to justify the performance. By adjusting output currents, the slew rate of output signal could be compensated over 26% and the maximum data rate is 330 MHz. [ABSTRACT FROM PUBLISHER]

Published
2012
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3. A slew rate self-adjusting 2×VDD output buffer With PVT compensation.

Author

Chih-Lin Chen, Hsin-Yuan Tseng, Kuo, Ron-Chi, and Wang, Chua-Chin

Abstract

A novel PVT (Process, Voltage, Temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, voltage, and temperature deviation could be detected, respectively. The proposed design is implemented using a typical 90 nm CMOS process to justify the performance. By adjusting output currents, the slew rate of output signal could be compensated over 38% and the maximum data rate with compensation is 345 MHz. [ABSTRACT FROM PUBLISHER]

Published
2012
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5. On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2\,\times\,VDD Output Buffers.

Author

Wang, Chua-Chin, Chen, Chih-Lin, Kuo, Ron-Chi, Tseng, Hsin-Yuan, Liu, Jen-Wei, and Juan, Chun-Ying

Subjects
COMPLEMENTARY metal oxide semiconductors, THRESHOLD voltage, ELECTRIC potential, VERY large scale circuit integration, ELECTRIC currents
Abstract

A novel process and temperature compensation design for 2\,\times\,VDD output buffers is proposed, where the threshold voltages (Vth) of PMOSs and NMOSs varying with process and temperature deviation could be detected, respectively. A prototype 2\,\times\,VDD output buffer using the proposed compensation design is fabricated using a typical 0.18 \mum CMOS process. By adjusting output currents, the slew rate of output signals could be compensated over 117%. The maximum data rate with compensation is 120 MHz in contrast with 95 MHz without compensation, which is measured on silicon with an equivalent probe capacitive load of 10 pF. [ABSTRACT FROM PUBLISHER]

Published
2013
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