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Objective - To determine if using ear plugs reduce the impact of noise on preterm babies admitted to neonatal intensive care units in terms of changes in their vital parameters and their discomfort level, assessed using the Neonatal Infant Pain Scale (NIPS) score. Materials and Methods - This is an interventional study conducted in a tertiary level neonatal intensive care unit (NICU) (Bangalore, India) over a period of 3 months, ranging from June 2022 to September 2022. This study included 20 preterm babies with different gestational ages and birth weights who were admitted to the NICU during that period. The babies' response to noise, in terms of changes in heart rate, respiratory rate, blood pressure, oxygen saturation and discomfort level, were assessed with ear plugs and without ear plugs on alternate days and the results were recorded. Descriptive statistics were used for statistical analysis. Results - On days 1 and 3, mean heart rate and systolic blood pressure were lower in babies wearing ear plugs (141.55±2.42 SD and 60.1±11.58, respectively) than in the same babies without ear plugs (157.55±2.52 SD and 61.85±1.6 SD, respectively) on days 2 and 4. The mean oxygen saturation was higher in babies wearing ear plugs (96.7%±0.80 SD) than in the same babies without the intervention (93.75%±1.29 SD). The mean NIPS score was lower with the intervention (2.05±0.22) than without ear plugs (5.05±0.22 SD). Conclusion - Ear plugs were an effective alternative in situations where noise in the NICU cannot be consistently maintained at a lower level than the standard recommendation by the AAP of 45 decibels. [ABSTRACT FROM AUTHOR]

Apart from variable switching frequency, a major issue in direct torque controlled (DTC) induction motor drives is the high torque ripple, which can be minimized by incorporating suitable pulsewidth modulation schemes such as space vector pulsewidth modulation (DTC-SVPWM) and duty ratio control DTC. However, the simplicity and robustness of the DTC scheme are compromised due to the high computational complexity and requirement of a number of motor parameters for the control. In this article, a simple and elegant control algorithm for the realisation of the DTC-SVPWM that is less dependent on motor parameters is proposed. The stator flux-linkage space vector angle needed to generate the reference torque for the DTC operation is computed based on the basic torque equation and the reference stator phase voltage needed for the SVPWM is determined in turn in every sampling period. For the modulation, a carrier-based space vector pulsewidth modulation (CSVPWM) scheme is adopted to get low torque ripple at constant switching frequency. The proposed speed control scheme avoids the use of rotor parameters and rotating reference frame transformations. It requires no sector identification and only one PI controller is needed for the speed control. Though the scheme has comparable torque ripple as that of the conventional DTC-SVPWM scheme, it significantly reduces the computational burden. Hardware results on a three-phase, 2 HP, 415 V induction motor are presented to validate the performance of the proposed control scheme. [ABSTRACT FROM AUTHOR]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

Voltage source inverter (VSI)-fed six-phase induction motor (IM) drives have high $6n\pm 1$, n = \odd-order harmonic currents. This is because these currents, driven by the corresponding harmonic voltages in the inverter output, are limited only by the stator leakage impedance, as these harmonics are absent in the back electromotive force of the motor. To suppress the harmonic currents, either bulky inductive harmonic filters or complex pulsewidth modulation (PWM) techniques have to be used. This paper proposes a harmonic elimination scheme using switched capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase inverters fed from capacitors are used on the open-end side of the motor to suppress $6n\pm 1$, n = \odd-order harmonics. A PWM scheme that can suppress the harmonics as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected, and the fundamental power is always drawn from the main inverters. The proposed scheme is verified with a detailed experimental study. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. [ABSTRACT FROM PUBLISHER]

In this paper, a current error space vector (CESV)-based hysteresis current controller for a multilevel 12-sided voltage space vector-based inverter-fed induction motor (IM) drive is proposed. The proposed controller gives a nearly constant switching frequency operation throughout different speeds in the linear modulation region. It achieves the elimination of 6n \pm 1, n = odd harmonics from the phase voltages and currents in the entire modulation range, with an increase in the linear modulation range. It also exhibits fast dynamic behavior under different transient conditions and has a simple controller implementation. Nearly constant switching frequency is obtained by matching the steady-state CESV boundaries of the proposed controller with that of a constant switching frequency SVPWM-based drive. In the proposed controller, the CESV reference boundaries are computed online, using the switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages. Vector change is decided by projecting the actual current error along the computed hysteresis space vector boundary of the presently applied vector. The estimated reference phase voltages are found from the stator current error ripple and the parameters of the IM. [ABSTRACT FROM PUBLISHER]

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n ± 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including overmodulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally. [ABSTRACT FROM AUTHOR]

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept. [ABSTRACT FROM PUBLISHER]