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In this paper, a novel high-speed and energy-efficient 4–2 compressor cell is proposed using carbon nanotube field-effect transistors. The proposed compressor is realized efficiently based on NAND–NOR gates and multiplexers. To estimate the performance of the presented design, simulations are carried out using Synopsis HSPICE under different conditions. The results demonstrate the improvement of the proposed design compared to the best reference designs in terms of delay and energy consumption, by 20–26%, respectively. Also, the susceptibility of the proposed design against the process, voltage, temperature (PVT), and noise variations is examined. It is robust against PVT variations and high amplitude of noises compared with its counterpart. Further, embedding the proposed compressor in an 8 × 8-bit binary multiplier demonstrates that it has better speed and energy consumption with regard to its counterparts. [ABSTRACT FROM AUTHOR]

The review highlights possible research topics matching the experimental physics of matter with advances in electronics to improve the intelligent design and control of innovative smart materials. Specifically, following the European research guidelines of Key Enabling Technologies (KETs), I propose different topics suitable for project proposals and research, including advances in nanomaterials, nanocomposite materials, nanotechnology, and artificial intelligence (AI), with a focus on electronics implementation. The paper provides a new research framework addressing the study of AI driving electronic systems and design procedures to determine the physical properties of versatile materials and to control dynamically the material's "self-reaction" when applying external stimuli. The proposed research framework allows one to ideate new circuital solutions to be integrated in intelligent embedded systems formed of materials, algorithms and circuits. The challenge of the review is to bring together different research concepts and topics regarding innovative materials to provide a research direction for possible AI applications. The discussed research topics are classified as Technology Readiness Levels (TRL) 1 and 2. [ABSTRACT FROM AUTHOR]

Density Functional Theory is utilized to scrutinize the electronic state of silicene and boron nano-onion which is a round compact mass formed by placing an N20, C20, and B20 fullerene within its parent atom fullerene B40. The NEGF is used to investigate the quantum transport at both equilibrium and non-equilibrium. Firstly the I-V curve for both silicene and boron-based devices is studied. From the results, it is concluded that boron-based devices are better than silicene. Therefore to get deeper insights into why boron-based devices are better transport properties of boron-based devices are suited. Later on, the transport mechanism is analyzed by computing the DOS, transmission and molecular spectra, HLG, I-V curve, electron densities, and differential conductance. When the Boron nano-onion is placed between the pair of Au electrodes. The calculated results are evaluated and a comparative study is done. From the results, it is deduced that the N20 variant nano-onion has reduced the HOMO-LUMO gap (HLG) and highest value of current in comparison to other devices. Thus by infusing a smaller fullerene of N20 inside the hollow cage of B40 fullerene the amplification of current and conductance can be observed in Boron-nano-onion in comparison to other devices. [ABSTRACT FROM AUTHOR]

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs' correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs. [ABSTRACT FROM AUTHOR]

In this paper, a new method for implementing all two-input logic gates on an identical single-stage structure is proposed. We have used unique characteristics of single-electron transistors, which have periodic output–input relation, to design the gates and implement all two-input logic gates (symmetric/non-symmetric, monotonic/non-monotonic) by a single-stage design including only one single-electron transistor. In conventional monotonic devices, such as BJTs and MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible with a single-stage circuit and a multistage design is required which leads to more complexity, more chip area and higher power consumption. We present the proposed methodology at first, and then, the details of the designs are investigated. The results are obtained analytically using a new approach named two-potential and then confirmed by numerical methods. Furthermore, important characteristics of the proposed gates such as maximum operating temperature, speed of the gates and frequency limitations, power consumption (static and dynamic) and scaling to other technologies have been investigated. Finally, a general idea has been presented about the application of the introduced approach and gate structures in the field of logic circuit and system designing. [ABSTRACT FROM AUTHOR]

A combination of computational power provided by modern MOSFET-based devices with light assisted wideband communication at the nanoscale can bring electronic technologies to the next level. Obvious obstacles include a size mismatch between electronic and photonic components as well as a weak light–matter interaction typical for existing devices. Polariton modes can be used to overcome these difficulties at the fundamental level. Here, we review applications of such modes, related to the design and fabrication of electro–optical circuits. The emphasis is made on surface plasmon-polaritons which have already demonstrated their value in many fields of technology. Other possible quasiparticles as well as their hybridization with plasmons are discussed. A quasiparticle-based paradigm in electronics, developed at the microscopic level, can be used in future molecular electronics and quantum computing. [ABSTRACT FROM AUTHOR]

In this paper, a low-power high-speed hybrid full adder cell is proposed, which is implemented based on two-input multi-threshold (Vt) XNOR circuit and transmission gate multiplexers. In order to implement this circuit, carbon nanotube field-effect transistors are utilized. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects of digital circuits: power, delay and power-delay product. The results are presented and confirm the superiority of the proposed cell with the previously reported one in different voltage levels, load conditions, temperatures and robustness in large structures and against process variations. [ABSTRACT FROM AUTHOR]

Multi-Gate FET (MGFET) device technology is the most promising technology for extending Moore's Law all the way down to 5nm. Besides being fully compatible with CMOS in both bulk and SOI varieties, MGFET device technology offers excellent solution to the problems of tunnelling carriers through ultra-thin gate dielectrics, short-channel effects, degraded sub-threshold performance and eventual quantum-mechanical effects that plagued planar CMOS as it is scaled down towards 20nm. Furthermore, it offers the ability to operate at much lower supply voltages and allows both static and dynamic power savings. In this paper. Common-mode (CM) MGFETs for three technology nodes (32nm, 22nm and 16nm) were simulated using SPICE simulator and compared for various performance characteristics. The variation in performance parameters was studied and compared for Double-Gate (DG), Triple-Gate (TG) and Gate-All-Around (GAA) to verify their scope for analogue and digital applications. In addition, the comparative results and performance parameters of CM MGFETs based logic gates for the three technology nodes are also presented. [ABSTRACT FROM AUTHOR]

This article investigates the aspects of designing a nanocell based molecular memory. An empirical model for molecular device is developed, based on circuit behavior of nitro-substituted Oligo (Phynylene Ethynylene) molecule (OPE). This device model is subsequently used to design nanocell based 1-bit memory and verified using HSPICE. The approach is extended to train the nanocell for multibit storage capability using external voltage signals. It is observed that to successfully train a 2-bit molecular memory, the number of control signals should be approx. one-fourth of total number of nanoparticles. A computational framework is proposed to compute the probability of retrieving the stored data bits correctly, at the output terminal of the nanocell buffer. This nanocell configuration is simulated by systematically varying number of nanoparticles and molecular switches. It is observed that the probability of the existence of at least one path from input to output approaches close to unity with presence of 20 or more nanoparticles in a nanocell. During memory model validation, 1000 samples of 1-bit memory (consisting of 20 nanoparticles) were generated and verified for read and write operations. The model verification results obtained for this memory cell closely match those obtained using analytical solution of probabilistic graph model. [ABSTRACT FROM AUTHOR]

This work explores anti-serial (anti-parallel) memristive switches-ASMs (APMs)-as potential cross-point elements in nano-crossbar resistive random access memory arrays. The memory operation principles for both device combinations are shown in detail. The effectiveness of these memristive structures to the solution of the parasitic conducting (current sneak paths) problem is presented via an analytical approach which is based on the basic setup of resistive crossbar memories. Simulation results of crossbars of up to 4,096 elements, arranged in quadratic configurations, are conducted. The provided results supplement this comprehensive analysis of APMs and ASMs, outlining their overall performance characteristics and commenting on their applicability to the practical realization of large crossbar memory systems. Finally, a special array topology is applied to an ASM-based crossbar memory. Its performance is compared to the performance of the pure ASM-based memory. The conducted simulations reveal significantly improved read-out voltage margins which further contribute to addressing the parasitic current paths which prevent the reliable operation of memristive crossbar circuit topologies. [ABSTRACT FROM AUTHOR]

The Vertical Strained SiGe Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The effect of doping concentration for both Source and Drain (S/D) as well as body doping concentration to the performance of VESIMOS-DP in terms of subthreshold slope (S), threshold voltage (VTH) and drain current has been observed in this paper. An inverse proportional of S and VTH value was found when S/D doping concentration increased. It is notable that for S/D doping concentration above 1019 atoms/cm3, there is a significant increase in S values which is not recommended as the switching speed getting higher distracting performance of the device. However, too low S/D doping concentration is not essential as it didn't show any significant improvement on the performance of the device. It is also revealed that with low body doping concentration, the device suffers tremendous Parasitic Bipolar Transistor (PBT) effect that prevents the device from switched off. Thus, optimum doping concentration is imperative to obtain superb device characteristic. Due to the DP layer, a stable VTH =1.35V obtained due to the vicinity of DP layer near the drain end has reduced charge sharing between the source and drain. The slight different and consistency of VESIMOS-DP subthreshold value (S = 19 mV/dec) has given advantages for incorporating DP layer near the drain end. In many aspects, it is revealed that the incorporation of DP has enhanced the electrical performance and suppressed PBT effect of IMOS in the nanometer regime for future development of nanoelectronic device. [ABSTRACT FROM AUTHOR]

A generation of optical capsules and tweezers within a modified optical add-drop filter known as PANDA ring resonator with a new concept is proposed. By using dark and bright solitons, the orthogonal tweezers can be formed within the system and observed simultaneously at the output ports. Under the resonant condition, the optical capsules and tweezers generated by dark and bright soliton pair corresponding to the left-hand and right-hand rotating solitons (tweezers) can be generated. When a soliton is interacted by an object, an angular momentum of either bright or dark tweezers is imparted to the object, in which two possible spin states known as tweezer spins are exhibited. Furthermore, an array of molecular capsules and spins, i.e., trapped molecules can be generated and detected by using the proposed system, which can be used to form large scale tweezer or capsule spins. In application, the trapped molecules can be moved and rotated securely to the required destinations, which can be useful for many applications, especially, in medical diagnosis, therapy and surgery. [ABSTRACT FROM PUBLISHER]

Several emerging nano-technologies, including crossbar nano-architectures, have recently been studied as possible replacement or supplement to CMOS technology in the future. However, extreme process variation and high failure rates, mainly due to atomic device sizes, are major challenges for crossbar nanoarchitectures. This article presents variation- and defect-tolerant logic mapping on crossbar nano-architectures. Since variation/defect-aware mapping is an NP-hard problem, we introduce a set of Integer Linear Programming (ILP) formulations to effectively solve the problem in a reasonable time. The proposed ILP formulations can be used for both diode-based and FET-based crossbars. Experimental results on benchmark circuits show that our approach can reduce the critical-path delay 39% compared to the Simulated Annealing (SA) method. It can also successfully achieve 97% defect-free mapping with 40% defect density. It can tolerate process variations to meet timing constraints in 95% of the cases, compared to only 77% achieved by SA. [ABSTRACT FROM AUTHOR]

The article discusses the Molecular Architectures for Quantum-dot Cellular Automata (QCA)-Inspired Boolean Network (MolArNet) project. It informs that the project is based on QCA which involves confinement and tunneling of quantum charge and also electrostatic interactions for the implementation of digital computation. The aim of the project is to take realistic steps and out of the laboratory implementation of molecular QCA.

In the field of Si nanoscale ultralarge-scale integration, the quantum confinement effect is undesirable with respect to the device characteristics and performance because the carriers are entirely confined in nanoscale or low-dimensional structures. Significant efforts are being made with regard to the positive use of the quantum confinement effect in Si nanoscale structures. One such attempt is related to the use of Si optoelectronics and photonics for optical interconnections within a Si chip. In this study, the intrinsic electronic structures in the Si-based nanostructures with different dimensions and sizes as candidates for Si optoelectronics were investigated by the DV-Xα molecular orbital calculation, which is advantageous to simulate the valence band structures for nanomaterials. We discuss the shift of a light emission peak to a higher energy due to the quantum confinement of carriers in the Si-based nanostructures, which depends on the sizes and numbers of structural dimensions, on the basis of the calculated results. Also, effect of doping of group IIIB and VB elements in the periodic table on the extrinsic electronic structures of the Si-based nanostructures were clarified by combining the Vienna ab-initio code for determining the relaxation structures around the dopants with the DV-Xα method for simulating the valence band structures. The results obtained are useful as a measure of possibility of the Si-based nano-structured materials for optoelectronics. © 2009 Wiley Periodicals, Inc. Int J Quantum Chem, 2009 [ABSTRACT FROM AUTHOR]

This paper reports on progress made in the first 3 years of ATR's 'CAM-Brain' Project, which aims to use 'evolutionary engineering' techniques to build/grow/evolve a RAM-and-cellular-automata based artificial brain consisting of thousands of interconnected neural network modules inside special hardware such as MIT's Cellular Automata Machine 'CAM-8', or NTT's Content Addressable Memory System 'CAM-System'. The states of a billion (later a trillion) 3D cellular automata cells, and millions of cellular automata rules which govern their state changes, can be stored relatively cheaply in giga(tera)bytes of RAM. After 3 years work, the CA rules are almost ready. MIT's 'CAM-8' (essentially a serial device) can update 200,000,000 CA cells a second. It is possible that NTT's 'CAM-System' (essentially a massively parallel device) may be able to update a trillion CA cells a second. Hence all the ingredients will soon be ready to create a revolutionary new technology which will allow thousands of evolved neural network modules to be assembled into artificial brains. This in turn will probably create not only a new research field, but hopefully a whole new industry, namely 'brain building'. Building artificial brains with a billion neurons is the aim of ATR's 8 year 'CAM-Brain' research project, ending in 2001. [ABSTRACT FROM AUTHOR]