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In this paper we deposit structures comprising a stack of 10 periods made of 15-nm-thick Ge multiple quantum wells (MQWs) enclosed in a 15-nm-thick Si0.2Ge0.8 barrier on SiGe virtual substrates (VSs) featuring different Ge content in the 85%–100% range to investigate the influence of heteroepitaxial strain on Si0.2Ge0.8 and Ge growth. With increasing Ge concentration of the VS, the growth rate of Si0.2Ge0.8 in the MQWs increases. Si incorporation into the Si0.2Ge0.8 layer also becomes slightly higher. However, almost no influence of the growth rate is observed for Ge growth in the MQWs. We argue that increased tensile strain promotes the Si reaction at the surface. In the case of Si0.2Ge0.8 growth on Ge, we observe a smeared interface due to Ge segregation during the growth. Furthermore, we observe that the interface width increases with increasing Ge concentration of the VS. We attribute this observation to the increased segregation of Ge driven by increased strain energy accumulated in the Si0.2Ge0.8 layers. We also observe that the MQW layer “filters out” threading dislocations formed in the VS. [ABSTRACT FROM AUTHOR]

We investigate the distribution of Sn in GeSn nano-heteroepitaxial clusters deposited at temperatures well exceeding the eutectic temperature of the GeSn system. The 600 °C molecular beam epitaxy on Si-patterned substrates results in the selective growth of GeSn nano-clusters having a 1.4 ± 0.5 at% Sn content. These nano-clusters feature Sn droplets on their faceted surfaces. The subsequent deposition of a thin Ge cap layer induced the incorporation of the Sn atoms segregated on the surface in a thin layer wetting the nano-dots surface with 8 ± 0.5 at% Sn. The presence of this wetting layer is associated with a relatively strong photoluminescence emission that we attribute to the direct recombination occurring in the GeSn nano-dots outer region. [ABSTRACT FROM AUTHOR]

We present the nanoheteroepitaxial growth of gallium arsenide (GaAs) on nano-patterned silicon (Si) (001) substrates fabricated using a CMOS technology compatible process. The selective growth of GaAs nano-crystals (NCs) was achieved at 570 °C by MOVPE. A detailed structure and defect characterization study of the grown nano-heterostructures was performed using scanning transmission electron microscopy, x-ray diffraction, micro-Raman, and micro-photoluminescence (μ-PL) spectroscopy. The results show single-crystalline, nearly relaxed GaAs NCs on top of slightly, by the SiO2-mask compressively strained Si nano-tips (NTs). Given the limited contact area, GaAs/Si nanostructures benefit from limited intermixing in contrast to planar GaAs films on Si. Even though a few growth defects (e.g. stacking faults, micro/nano-twins, etc) especially located at the GaAs/Si interface region were detected, the nanoheterostructures show intensive light emission, as investigated by μ-PL spectroscopy. Achieving well-ordered high quality GaAs NCs on Si NTs may provide opportunities for superior electronic, photonic, or photovoltaic device performances integrated on the silicon technology platform. [ABSTRACT FROM AUTHOR]

Nano-heteroepitaxial growth of GaAs on Si(001) by metal organic vapor phase epitaxy was investigated to study emerging materials phenomena on the nano-scale of III–V/Si interaction. Arrays of Si nano-tips (NTs) embedded in a SiO2 matrix were used as substrates. The NTs had top Si openings of 50–90 nm serving as seeds for the selective growth of GaAs nano-crystals (NCs). The structural and morphological properties were investigated by high resolution scanning electron microscopy, atomic force microscopy, electron backscatter diffraction, x-ray diffraction, and high resolution scanning transmission electron microscopy. The GaAs growth led to epitaxial NCs featuring a bi-modal distribution of size and morphology. NCs of small size exhibited high structural quality and well-defined {111}–{100} faceting. Larger clusters had less regular shapes and contained twins. The present work shows that the growth of high quality GaAs NCs on Si NTs is feasible and can provide an alternate way to the integration of compound semiconductors with Si micro- and opto-electronics technology. [ABSTRACT FROM AUTHOR]