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The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems. [ABSTRACT FROM AUTHOR]

Real-time inference of deep learning models on embedded and energy-efficient devices becomes increasingly desirable with the rapid growth of artificial intelligence on edge. Specifically, to achieve superb energy-efficiency and scalability, efficient parallelization of single-pass deep neural network (DNN) inference on chip multiprocessor (CMP) architectures is urgently required by many time-sensitive applications. However, as the number of processing cores scales up and the performance of cores has grown much fast, the on-chip inter-core data movement is prone to be a performance bottleneck for computation. To remedy this problem and further improve the performance of network inference, in this work, we introduce a communication-aware DNN parallelization technique called CAP, by exploiting the elasticity and noise-tolerance of deep learning algorithms on CMP. Moreover, in the hope that the conducted studies can provide new design values for real-time neural network inference on embedded chips, we also have evaluated the proposed approach on both multi-core Neural Network Accelerators (NNA) chips and general-purpose chip-multiprocessors. Our experimental results show that the proposed CAP can achieve 1.12×-1.65× system speedups and 1.14×-2.70× energy efficiency for different neural networks while maintaining the inference accuracy, compared to baseline approaches. [ABSTRACT FROM AUTHOR]

Mechatronic systems, like mobile robots, are fairly complex. They are composed of electromechanical actuation components and sensing elements supervised by microcontrollers running complex embedded software. This paper proposes a novel approach to aid mobile robotics developers in adopting a rigorous development process to design and verify the robot's detection and mitigation capabilities against random hardware failures affecting its sensors or actuators. Unfortunately, assessing the interactions between the various safety/mission-critical subsystem is quite complex. The failure mode effect analysis (FMEA) alongside an analysis of the failure detection capabilities (FMEDA) are the state-of-the-art methodologies for performing such an analysis. Various guidelines are available, and the authors decided to follow the one released by AIAG&VDA in June 2019. Since the robot's behavior is based on embedded software, the FMEA has been integrated with the hardware/software interaction analysis described in the ECSS-Q-ST-30-02C manual. The core of this proposal is to show how a simulation-based approach, where the mechanical and electrical/electronic components are simulated alongside the embedded software, can effectively support FMEA. As a benchmark application, we considered the mobility system of a proof-of-concept assistance rover for Mars exploration designed by the D.I.A.N.A. student team at Politecnico di Torino. Thanks to the adopted approach, we described how to develop the detection and mitigation strategies and how to determine their effectiveness, with a particular focus on those affecting the sensors. [ABSTRACT FROM AUTHOR]

Emerging safety-critical systems require high-performance data-parallel architectures and, problematically, ones that can guarantee tight and safe worst-case execution times. Given the complexity of existing architectures like GPUs, it is unlikely that sufficiently accurate models and algorithms for timing analysis will emerge in the foreseeable future. This motivates our work on Sim-D, a clean-slate approach to designing a real-time data-parallel architecture. Sim-D enforces a predictable execution model by isolating compute- and access resources in hardware. The DRAM controller uninterruptedly transfers tiles of data, requested by entire work-groups. This permits work-groups to be executed as a sequence of deterministic access- and compute phases, scheduling phases from up to two work-groups in parallel. Evaluation using a cycle-accurate timing model shows that Sim-D can achieve performance on par with an embedded-grade NVIDIA TK1 GPU under two conditions: applications refrain from using indirect DRAM transfers into large buffers, and Sim-D's scratchpads provide sufficient bandwidth. Sim-D's design facilitates derivation of safe WCET bounds that are tight within 12.7 percent on average, at an additional average performance penalty of $\sim$ ∼ 9.2 percent caused by scheduling restrictions on phases. [ABSTRACT FROM AUTHOR]

In this article, we present an Online Learning Artificial Neural Network (ANN) model that is able to predict the performance of tasks in lower frequency levels and safely optimize real-time embedded systems’ power saving operations. The proposed ANN model is supported by feature selection, which provides the most relevant variables to describe shared resource contention in the selected multicore architecture. The variables are used at runtime to produce a performance trace that encompasses sufficient information for the ANN model to predict the impact of a frequency change on the performance of tasks. A migration heuristic encompassing a weighted activity vector is combined with the ANN model to dynamically adjust frequencies and also to trigger task migrations among cores, enabling further optimization by solving resource contentions and balancing the load among cores. The proposed solution achieved energy-savings of 24.97 percent on average when compared to the run-to-end approach, and it did it without compromising the criticality of any single task. The overhead incurred in terms of execution time was 0.1791 percent on average. Each prediction added 15.3585 $\mu s$ μ s on average and each retraining cycle triggered at frequency adjustments was never larger than 100 $\mu s$ μ s . [ABSTRACT FROM AUTHOR]

The exact response time analysis for fixed priority scheduling (FPS) in the lowest priority first-based feasibility tests is commonly required as a part of system design tools. This letter proposes an efficient method for this, which we named incremental lower bound (ILB) calculation method. Compared to the best algorithm that has been known so far, which is the incremental calculation method, ILB reduces the feasibility test iterations/run times by more than 38% and 20% regardless of varying utilization and the number of tasks in task sets. [ABSTRACT FROM AUTHOR]

Real-time and embedded systems are required to adapt their behavior and structure to runtime unpredicted changes in order to maintain their feasibility and usefulness. These systems are generally more difficult to specify and verify owning to their execution complexity. Hence, ensuring the high-level design and the early verification of system adaptation at runtime is very crucial. However, existing runtime model-based approaches for adaptive real-time and embedded systems suffer from shortcoming linked to efficiently and correctly managing the adaptive system behavior, especially that a formal verification is not allowed by modeling languages such as UML and MARTE profile. Moreover, reasoning about the correctness and the precision of high-level models is a complex task without the appropriate tool support. In this work, we propose an MDE-based framework for the specification and the verification of runtime adaptive real-time and embedded systems. Our approach stands for Event-B method to formally verify resources behavior and real-time constraints. In fact, thanks to MDE M2T transformations, our proposal translates runtime models into Event-B specifications to ensure the correctness of runtime adaptive system properties, temporal constrains and nonfunctional properties using Rodin platform. A flood prediction system case study is adopted for the validation of our proposal. [ABSTRACT FROM AUTHOR]

The ever-increasing need for computational power in embedded devices has led to the adoption heterogeneous SoCs combining a general purpose CPU with a data parallel accelerator. These systems rely on a shared main memory (DRAM), which makes them highly susceptible to memory interference. A promising software technique to counter such effects is the Predictable Execution Model (PREM). PREM ensures robustness to interference by separating programs into a sequence of memory and compute phases, and by enforcing a platform-level schedule where only a single processing subsystem is permitted to execute a memory phase at a time. This article demonstrates for the first time how PREM can be applied to heterogeneous SoCs, based on a synchronization technique for memory isolation between CPU and GPU plus a compiler to transform GPU kernels into PREM-compliant codes. For compute bound GPU workloads sharing the DRAM bandwidth 50/50 with the CPU we guarantee near-zero timing varibility at a performance loss of just 59 percent, which is one to two orders of magnitude smaller than the worst case we see for unmodified programs under memory interference. [ABSTRACT FROM AUTHOR]

Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the cache circuits, hence significantly reduces the cache access latency. The performance, hardware and power overheads due to the proposed prioritized LRU circuits are investigated based on a 65 nm CMOS technology. It shows that the proposed circuits have very low overhead compared to conventional cache circuits. The presented techniques will lead to more effective prioritized shared cache implementations and benefit the development of high-performance real-time systems. [ABSTRACT FROM AUTHOR]

The importance of physically contiguous memory has increased in modern computing environments, including both low- and high-end systems. Existing physically contiguous memory allocators generally have critical limitations. For example, the most commonly adopted solution, the memory reservation technique, wastes a significant amount of memory space. Scatter/Gather direct memory access (DMA) and input-output memory management units (IOMMUs) avoid this problem by utilizing additional hardware for address space virtualization. However, additional hardware means an increase in costs and power consumption, which is especially disadvantageous for small systems and they do not provide real contiguous memory. Linux Contiguous Memory Allocator (CMA) aims to provide both contiguous memory allocation and to maximize memory utilization based on page migration, but they suffer from unpredictably long latency and a high probability of allocation failure. Therefore, we introduce a new solution to this problem, the guaranteed contiguous memory allocator (GCMA). This guarantees efficient memory space utilization, short latency, and successful allocation. The GCMA uses a reservation scheme and increases memory utilization by sharing the memory with immediately discardable data. Our evaluation of a GCMA on a Raspberry Pi 2 finds a latency that is 15-130 times lower compared to a CMA, and a latency that is up to 10 times lower when taking a photo. Using a large working set in a memory-fragmented high-end system, the GCMA is able to produce a 2.27x speedup. [ABSTRACT FROM AUTHOR]

This paper introduces a new technique that perturbs split-gate NOR Flash memory cells and extracts randomness of read noise to generate true random numbers. Flash memory cells exhibit threshold voltage fluctuations during read operations caused by thermal noise and random telegraph noise effects. Recent proposals demonstrate how these inherent properties of Flash memory cells can be used to create true random numbers in modern NAND Flash memories. However, they cannot be directly applied to NOR Flash memories in microcontrollers that have different architecture, improved data retention, high endurance, and are not as susceptible to noise as high-density NAND Flash memories. The proposed technique is experimentally demonstrated and evaluated using a family of commercial microcontrollers. The evaluation shows that it enables extraction of high-throughput random sequences that pass the NIST statistical tests. Advantages of the proposed technique are as follows: (a) it does not require any special hardware and/or interface modifications, (b) it is robust, cost-effective, and high-throughput, (c) it is entirely implemented in software, and (d) it is flexible and can be tailored to work in low-end microcontrollers that are often resource- or cost-constrained. [ABSTRACT FROM AUTHOR]

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm capable of high accuracy rates for a different range of applications. When arranged in a cascade structure, SVMs can efficiently handle problems where the majority of data belongs to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, the SVM classification process is still computationally demanding due to the number of support vectors. Consequently, in this paper we propose a hardware architecture optimized for cascaded SVM processing to boost performance and hardware efficiency, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings. The architecture was evaluated for the application of object detection on 800×600 resolution images on a Spartan 6 Industrial Video Processing FPGA platform achieving over 30 frames-per-second. Moreover, by utilizing the proposed hardware reduction method we were able to reduce the utilization of FPGA custom-logic resources by ∼30%, and simultaneously observed ∼20% peak power reduction compared to a baseline implementation. [ABSTRACT FROM AUTHOR]

Many high-level vision applications apply image segmentation during preprocessing to improve their overall execution efficiency. The applied segmentation technique must, therefore, be highly efficient, or otherwise would counteract any system performance improvement. Existing segmentation approaches often fail to meet real-time processing standards and exhibit extremely slow frame rates when applied to high-resolution images. This paper presents a highly optimized serial implementation of a novel image segmentation approach known as leap segmentation, which achieves frame rates exceeding that of the state-of-the art: it segments more than 80 fps on 640 × 360 images and more than 20 fps on high-resolution (1,280 × 720) images. (All images used for evaluation in this paper use a 24-bit red-green-blue color representation with 8 bits per color). We analyze leap segmentation further for areas of possible parallelization and restructure it for use on a parallel processing system to achieve additional speed-up. On a multi-core, mobile processing system with four threads, our multi-core leap segmentation implementation achieves frame rates of over 114 fps on 640 × 360 images and more than 31 fps on 1,280 × 720 images, thus easily exceeding real-time processing standards. [ABSTRACT FROM AUTHOR]

Synchronous dynamic random access memories (SDRAMs) are widely employed in multi- and many-core platforms due to their high-density and low-cost. Nevertheless, their benefits come at the price of a complex two-stage access protocol, which reflects their bank-based structure and an internal level of explicitly managed caching. In scenarios in which requestors demand real-time guarantees, these features pose a predictability challenge and, in order to tackle it, several SDRAM controllers have been proposed. In this context, recent research shows that a combination of bank privatization and open-row policy (exploiting the caching over the boundary of a single request) represents an effective way to tackle the problem. However, such approach uncovered a new challenge: the data bus turnaround overhead. In SDRAMs, a single data bus is shared by read and write operations. Alternating read and write operations is, consequently, highly undesirable, as the data bus must remain idle during a turnaround. Therefore, in this article, we propose a SDRAM controller that reorders read and write commands, which minimizes data bus turnarounds. Moreover, we compare our approach analytically and experimentally with existing real-time SDRAM controllers both from the worst-case latency and power consumption perspectives. [ABSTRACT FROM PUBLISHER]

Energy efficiency is a challenging issue in autonomous and distributed sensing systems, especially when these systems are powered by renewable energy sources. In this paper, we present a link and energy adaptive UWB-based sensing technique to improve the detection time coverage and detection range coverage for self-sustained embedded applications. The basic idea is derived from the fact that domain-specific information in such applications is often available. Thus, by jointly exploiting the link information between the transmitter and receiver of the UWB pulse radar, and the non-deterministic characteristics of the renewable energy, the proposed technique dynamically adjusts the pulse repetition frequency of the UWB radar to enhance the sustainable operation under the unreliable energy supply. The overhead of the proposed technique is negligible as compared with the overall energy consumption of the UWB pulse radar. It was demonstrated that the proposed technique can achieve much better detection time coverage and detection range coverage than the conventional UWB radar. The proposed technique is also insensitive to many practical issues such as the limited battery capacity. [ABSTRACT FROM AUTHOR]

Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet the growing complexity of embedded applications with increasing computation parallelism. Particularly, real-time applications make out a significant portion of the embedded field. Networks-on-Chip (NoCs) are the backbone of communications in an MPSoC platform. However, the use of NoCs in real-time systems imposes complex constraints on the overall design. This paper discusses the challenges faced, when designing NoCs for real-time applications. Contributions in this area are surveyed on the level of guaranteed Quality-of-Service (QoS) support, adaptivity, and energy efficient techniques. Furthermore, the evaluation methodologies and experimental performance measurements of real-time NoCs are examined. This survey provides a comprehensive overview of existing endeavors in real-time NoCs and gives an insight towards future promising research points in this field. [ABSTRACT FROM AUTHOR]

Multi-core processors are increasingly popular because they yield higher performance, but they also present new challenges for hard real-time systems in that they make it much more difficult to estimate a task's worst-case execution time (WCET). Partitioned cache architecture is being used to ease the problem by providing an isolated execution environment for each thread. Although simple to implement and use, this method may be sub-optimal with respect to both energy consumption and performance since it prevents taking advantage of information shared across threads for both instructions and data. This work presents a new cache architecture termed SPACE (Semi-Partitioned CachE) that makes it possible to leverage information sharing, yielding in turn a tighter WCET. The SPACE architecture together with our new WCET algorithm can be used to maintain the predictability of the execution time of the parallel threads while reducing the overall energy consumption of the system. The new proposed cache architecture was implemented using Verilog and deployed on a Xilinx MicroBlaze multi-core design for testing, validation and measurements. The application level experiments were conducted using the Chronos tool for estimation and the Wattch/SimpleScalar simulator for execution. Using three real-time programs–a radar tracker, a DES encryption algorithm, and an FM radio–we showed that SPACE together with the enhanced WCET algorithm reduce the average system WCET of these applications by 31 percent and reduce the actual energy consumption by 18 percent in comparison with other cache architectures. [ABSTRACT FROM PUBLISHER]

On emerging multicore systems, task replication is a powerful way to achieve high reliability targets. In this paper, we consider the problem of achieving a given reliability target for a set of periodic real-time tasks running on a multicore system with minimum energy consumption. Our framework explicitly takes into account the coverage factor of the fault detection techniques and the negative impact of Dynamic Voltage Scaling (DVS) on the rate of transient faults leading to soft errors. We characterize the subtle interplay between the processing frequency, replication level, reliability, fault coverage, and energy consumption on DVS-enabled multicore systems. We first develop static solutions and then propose dynamic adaptation schemes in order to reduce the concurrent execution of the replicas of a given task and to take advantage of early completions. Our simulation results indicate that through our algorithms, a very broad spectrum of reliability targets can be achieved with minimum energy consumption thanks to the judicious task replication and frequency assignment. [ABSTRACT FROM PUBLISHER]

Real-time safety-critical systems should provide hard bounds on an applications’ performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers’ performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. [ABSTRACT FROM AUTHOR]

This paper proposes an N-modular redundancy (NMR) technique with low energy-overhead for hard real-time multi-core systems. NMR is well-suited for multi-core platforms as they provide multiple processing units and low-overhead communication for voting. However, it can impose considerable energy overhead and hence its energy overhead must be controlled, which is the primary consideration of this paper. For this purpose the system operation can be divided into two phases: indispensable phase and on-demand phase. In the indispensable phase only half-plus-one copies for each task are executed. When no fault occurs during this phase, the results must be identical and hence the remaining copies are not required. Otherwise, the remaining copies must be executed in the on-demand phase to perform a complete majority voting. In this paper, for such a two-phase NMR, an energy-management technique is developed where two new concepts have been considered: i) Block-partitioned scheduling that enables parallel task execution during on-demand phase, thereby leaving more slack for energy saving, ii) Pseudo-dynamic slack, that results when a task has no faulty execution during the indispensable phase and hence the time which is reserved for its copies in the on-demand phase is reclaimed for energy saving. The energy-management technique has an off-line part that manages static and pseudo-dynamic slacks at design time and an online part that mainly manages dynamic slacks at run-time. Experimental results show that the proposed NMR technique provides up to 29 percent energy saving and is 6 orders of magnitude higher reliable as compared to a recent previous work. [ABSTRACT FROM PUBLISHER]

Embedded systems are becoming pervasive in diverse domains, but their complexity and heterogeneity calls for new, efficient development methods to ensure their reliability and safety. The authors present a discrete-event modeling and simulation methodology based on solid mathematical theory to deal with these issues. The presented methodology also allows model-checking for verifying design properties. [ABSTRACT FROM AUTHOR]

Task switching, synchronization, and communication between processes are major problems for each real-time operating system. Software implementation of the specific mechanisms may lead to significant delays that can affect deadline requirements for some applications. This paper presents a hardware scheduler architecture integrated into the CPU structure that uses resource remapping techniques for the pipeline registers and for the CPU working registers. We present an original implementation of the hardware structure used for static and dynamic scheduling of the task, unitary management of events, access to architecture shared resources, event generation, and a method used for assigning interrupts to tasks that insures an efficient operation in the context of real-time control. One assembler instruction is used for simultaneous task synchronization with multiple event sources. This architecture allows a task switching time of one clock cycle (with a worst case scenario of three clock cycles for special instructions used for external memory accesses) and a response time of only 1.5 clock cycles for the events. Some mechanisms for improving program execution speed are also taken in consideration. [ABSTRACT FROM AUTHOR]

In high throughput applications, such as in multimedia, it is preferable to fully utilize computing resources, even at the price of some (bounded) delay. However, in real-time systems, where the maximum admissible delay is modeled by a deadline, most of the theory is developed with the assumption of a task deadline smaller than or equal to the task period. The reason of this limitation is in the intrinsic difficulty of the schedulability analysis in the arbitrary deadline case. The most notable guarantee test for sets of arbitrary deadline tasks was due to Lehoczky in 1990. In this paper, we propose the quadratic utilization bound applicable to tasks with arbitrary deadline, which extends Lehoczky’s result. The improvement is made possible by providing some information about the task periods. [ABSTRACT FROM AUTHOR]

An autonomous fault-tolerant system (AFTS) is one that can reconfigure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain the original functionality. This capability makes an AFTS especially suitable for use in harsh environments, where traditional electronics technology is susceptible to failure. This article describes the contributions of the Reliable Reconfigurable Real-Time Operating System (R3TOS) for building an AFTS using currently available Xilinx partially-reconfigurable field-programmable gate arrays. Namely, this article discusses what R3TOS offers for developing durable, dependable, and real-time embedded systems to be used in rugged environments. In this context, the article presents an R3TOS-based inverter controller of a real-world railway traction system that is proven to recover from most of the errors injected without requiring any human intervention. [ABSTRACT FROM PUBLISHER]

A novel method for a mobile phone centric observation of a user’s facing direction is presented. To estimate this direction, our proposed technique exploits the acceleration pattern that can be measured by a smartphone as the user is walking. For an accurate analysis of the acceleration pattern, the proposed approach benefits from a new trigonometric interpolation scheme. Our algorithm is independent of the initial orientation of the device and is adaptable to various wearing positions on a user’s body, which gives the user a larger degree of freedom. A detailed description of the algorithm, which has been customized for a trouser pocket is presented. In addition, complementary hints for adaptation of the algorithm to other wearing positions along with an example of chest pocket position are provided. We have evaluated a prototype implementation of our algorithm on a smartphone, through several field experiments. It has been observed that our algorithm outperforms the conventional GPS and PCA-based techniques in terms of accuracy, reliability and energy consumption. The results also show that our approach has been able to handle the sudden variations of the user’s direction. We have further incorporated our algorithm into a dead-reckoning application as an example of its real-world utility. [ABSTRACT FROM PUBLISHER]

This paper investigates the feasibility of real-time scheduling with mobile hypervisor, Xen-ARM. Particularly for mobile virtual machines, real-time support is in high demand. However, it is difficult to guarantee real-time scheduling with virtual machines because inter-VM and intra-VM schedulability have to be determined in multi-OS environments. To address the schedulability, first, this paper presents a definition of a real-time virtual machine. Second, this paper analyzes intra-VM schedulability, taking quantization overhead into account. Quantization overhead comes from tick-based scheduling of Xen-ARM, which requires integer presentation of scheduling period and execution slice. Third, to minimize quantization overhead, this paper provides a new algorithm, called SH-quantization that provides accurate and efficient parameterization of a real-time virtual machine. Fourth, this paper presents an inter-VM schedulability test for incorporating multiple real-time virtual machines. To evaluate the approach, we implement the SH-quantization algorithm in Xen-ARM and paravirtualize a real-time OS, called xeno- \(\mu \) C/OS-II. We ran extensive experiments with various configurations of real-time tasks on a real hardware platform in order to characterize the scheduling behavior of real-time virtual machine with quantization. The results show that quantization overhead consumes additional CPU bandwidth up to 90% and the proposed algorithm guarantees intra/inter-VM schedulability with minimal CPU bandwidth. [ABSTRACT FROM AUTHOR]

Incremental linear model trees with approximate lookahead are fast, but produce overly large trees. This is due to non-optimal splitting decisions boosted by a possibly unlimited number of examples obtained from a data source. To keep the processing speed high and the tree complexity low, appropriate incremental pruning techniques are needed. In this paper, we introduce a pruning technique for the class of incremental linear model trees with approximate lookahead on stationary data sources. Experimental results show that the advantage of approximate lookahead in terms of processing speed can be further improved by producing much smaller and consequently more explanatory, less memory consuming trees on high-dimensional data. This is done at the expense of only a small increase in prediction error. Additionally, the pruning algorithm can be tuned to either produce less accurate model trees at a much higher processing speed or, alternatively, more accurate trees at the expense of higher processing times. [ABSTRACT FROM PUBLISHER]

The use of components significantly helps in development of real-time embedded systems. There have been a number of component frameworks developed for this purpose, and some of them have already became well established in this area. Even though these frameworks share the general idea of component-based development, they significantly differ in the range of supported features and maturity. This makes it relatively difficult to select the right component framework and thus poses a significant obstacle in adoption of the component-based development approach for developing real-time embedded systems. To provide guidance in choosing a component framework, or at least relevant concepts when building a custom framework, we present a survey, which illustrates distinguishing features and provides comparison of selected modern component-based frameworks for real-time embedded systems. Compared to other existing surveys, this survey focuses specifically on criteria connected with real-time and embedded systems. Further, to be practically relevant, we restrict the survey only to the frameworks that support the full development life cycle (i.e. from design till execution support). In this context, the survey illustrates the complexity of development in each framework by giving specification and code samples. [ABSTRACT FROM AUTHOR]

The bus arrival time is primary information to most city transport travelers. Excessively long waiting time at bus stops often discourages the travelers and makes them reluctant to take buses. In this paper, we present a bus arrival time prediction system based on bus passengers' participatory sensing. With commodity mobile phones, the bus passengers' surrounding environmental context is effectively collected and utilized to estimate the bus traveling routes and predict bus arrival time at various bus stops. The proposed system solely relies on the collaborative effort of the participating users and is independent from the bus operating companies, so it can be easily adopted to support universal bus service systems without requesting support from particular bus operating companies. Instead of referring to GPS-enabled location information, we resort to more generally available and energy efficient sensing resources, including cell tower signals, movement statuses, audio recordings, etc., which bring less burden to the participatory party and encourage their participation. We develop a prototype system with different types of Android-based mobile phones and comprehensively experiment with the NTU campus shuttle buses as well as Singapore public buses over a 7-week period. The evaluation results suggest that the proposed system achieves outstanding prediction accuracy compared with those bus operator initiated and GPS supported solutions. We further adopt our system and conduct quick trial experiments with London bus system for 4 days, which suggests the easy deployment of our system and promising system performance across cities. At the same time, the proposed solution is more generally available and energy friendly. [ABSTRACT FROM PUBLISHER]

In this work, we present the design, development, and evaluation of a real-time target tracking system for wireless embedded nodes, capable of effectively tracking manoeuvring targets. The proposed tracking system is designed to operate solely on range measurements obtained with the use of a two-way time-of-flight method without the need for additional hardware being incorporated in the nodes. To address the challenge of coping with manoeuvring targets, the tracking problem is formulated as a dynamical estimation problem where an adaptive multiple-model approach is employed to represent the motion pattern of manoeuvring targets. The ranging observations are produced in real time and used as inputs to a particle filter algorithm that produces the estimates of the target's kinematic variables. Simulations are provided to assess the effect of several factors on the system's performance. Ultimately, the entire system is implemented on commercially available hardware and tested in an outdoor deployment. A total of 25 experiments demonstrate an average RMS accuracy of 2.6 m for position and 1.9 m/s for velocity, in a 15 m × 15 m area. Such performance, which is additionally confirmed from simulation results, reveals the potential of the proposed range-only system in application scenarios where real-time tracking of mobile targets is needed. [ABSTRACT FROM AUTHOR]

We propose an easy-to-implement hard-decision majority-logic decoding algorithm for Reed—Muller codes RM(r,m) with m ≥ 3, m/2 ≥ r≥ 1. The presented algorithm outperforms the best known majority-logic decoding algorithms and offers highly parallel decoding. The result is of special importance for safety- and time-critical applications in embedded systems. A simple combinational circuit can perform the proposed decoding. In particular, we show how our decoder for the three-error-correcting code RM(2, 5) of dimension 16 and length 32 can be realized on hardware level. [ABSTRACT FROM PUBLISHER]

A flash translation layer (FTL) provides file systems with transparent access to NAND flash memory. Although many applications running on it require real-time guarantees, it is difficult to provide tight worst case execution time (WCET) bounds with conventional static WCET analysis since an FTL exhibits a large variance in execution time depending on its runtime state. Parametric WCET analysis could be an effective alternative but it is also challenging to formulate a parametric WCET function for an FTL program because traditional FTL architecture does not properly model the runtime availability of flash resources in its code structure. To overcome such a limitation, we propose Petri net-based FTL architecture where a Petri net explicitly specifies dependencies between FTL operations and the runtime resource availability. It comes with an FTL operation sequencer that derives at runtime the shortest sequence of FTL operations for servicing an incoming FTL request under the current resource availability. The sequencer computes the WCET of the request by merely summing the WCETs of only those FTL operations in the sequence. Our experimental results show the effectiveness of our FTL architecture. It allowed for tight WCET estimation that yielded WCETs shorter by a factor of 54 than statically analyzed ones. [ABSTRACT FROM AUTHOR]

Since multicore architectures are becoming more popular, recent multicore optimizations focus on energy consumption. In this paper, we focus on reducing the energy consumption in the data and instruction cache hierarchies in a multicore system. First, we present a level one data cache tuning heuristic for a heterogeneous multicore system, which classifies applications based on data sharing and cache behavior and uses this classification to guide cache tuning and reduce the number of cores that need to be tuned. Results reveal average energy savings of 25 percent for 2, 4, 8, and 16-core systems while searching only 1 percent of the design space. Next, we present a level one instruction cache tuning heuristic that reduces energy consumption in the instruction cache hierarchy by an average of 53 percent for 2, 4, 8, and 16-core systems, while searching less than 1 percent of the design space. Finally, we develop a custom, global hardware cache tuner for a dual-core system and show that our cache tuner has low area, energy, and power overheads. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized processor architecture for Sobel edge detection operator on field programmable gate arrays (FPGA). The processor is optimized by the use of several optimization techniques that aim to increase the processor throughput and reduce the processor logic utilization. FPGA offers a high level of parallelism which is exploited by the processor to implement the parallel process of edge detection in order to increase the processor throughput and enable the processor to meet real-time performance constraints. To achieve real- time performance, the proposed processor consists of several Sobel instances that are able to produce massive output pixels in parallel. This parallelism enables data reuse within the processor block which reduces the number of calculations while increasing the processor throughput. Moreover, the processor gains performance with a factor equal to the number of instances contained in the processor block. By the application of the optimization techniques, the proposed Sobel processor is able to meet real-time performance constraints due to its high throughput even with a considerably low clock frequency. In addition, the logic utilization of the proposed processor is low compared to other Sobel processors when implemented on ALTERA Cyclone II DE2-70 board. [ABSTRACT FROM AUTHOR]

To estimate software code size early in the development process is important for developing cost-efficient embedded systems. We have applied the COSMIC Functional Size Measurement (FSM) method for size estimation of embedded software components in the automotive industry. Correlational studies were conducted using data from two automotive companies. The studies show strong correlation between functional size and software code size, which is important for obtaining accurate estimation results. This paper presents the characteristics and results of our work, and aims to provide a practical framework for how to use COSMIC FSM for size estimation purposes. We investigate the results from our earlier correlational studies, and conduct further studies to identify such a framework. Based on these activities, we conclude that a clear purpose of the estimation process, a well-defined domain allowing categorization of software, consistent content and quality of requirements, and historical data from implemented software are key factors for size estimation of embedded software components. [ABSTRACT FROM PUBLISHER]

Time-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware-redundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for low-energy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique to use standby sparing for hard real-time systems with limited energy budgets. The principal contribution of this paper is an online energy-management technique which is specifically developed for standby-sparing systems that are used in hard real-time applications. This technique operates at runtime and exploits dynamic slacks to reduce the energy consumption while guaranteeing hard deadlines. We compared the low-energy standby-sparing (LESS) system with a low-energy time-redundancy system (from a previous work). The results show that for relaxed time constraints, the LESS system is more reliable and provides about 26% energy saving as compared to the time-redundancy system. For tight deadlines when the time-redundancy system is not sufficiently reliable (for safety-critical application), the LESS system preserves its reliability but with about 49% more energy consumption. [ABSTRACT FROM AUTHOR]

In a multi-task embedded system, a cache is shared by different tasks, which increases the complexity of cache management and the unpredictability of cache behavior. This unpredictability in turn brings an overestimation of application's worst-case execution time (WCET) and worst-case CPU utilization (WCU) which are two of the most important criteria for real-time embedded systems. Modern processors often provide cache locking capability, which can be applied statically and dynamically to manage cache in a predictable manner. The selection of instructions to be locked in the instruction cache (I-Cache) has dramatic influence on the system performance. This paper focuses on applying cache locking techniques to the shared I-Cache to minimize WCU for multi-task embedded systems. We analyze and compare three different strategies to perform I-Cache locking: static locking, semi-dynamic locking, and dynamic locking. Different algorithms are proposed utilizing the foreknown information of embedded applications. Experimental results show that the proposed algorithms can reduce WCU compared to previous techniques. [ABSTRACT FROM AUTHOR]

The adoption of open-source operating systems for the execution of real-time applications is gaining popularity, even in the networked control systems domain, due to cost and flexibility reasons. However, as opposed to their commercial counterparts, the actual performance level to be expected from them is still little known and may often depend on the kind of real-time extension being used, its configuration, and the overall software load of the system, including best-effort components. [ABSTRACT FROM PUBLISHER]

Designers of embedded systems face tight constraints on resources, response time and cost. The ability to analyze embedded systems is essential to timely delivery of new designs. Many analysis techniques model parallel programs as task graphs. Task graphs capture the worst-case execution times of individual program tasks and the data dependencies among these. [ABSTRACT FROM PUBLISHER]

Contemporary teaching of real-time control, basic elements of which are part of a modern control engineering syllabus, can be restricted by the availability of laboratory space and the high costs of equipment, development tools and test beds. This paper describes RTE-SIM - a novel, flexible and low-cost environment developed by the authors to help alleviate these problems. The environment is in the form of an ARM7 microcontroller-based hardware-in-the-loop (HIL) environment. The paper describes each component in the HIL configuration, followed by an example of a typical student exercise. Most institutions can implement the proposed environment with few (if any) additional cost, space or time penalties incurred, and based on initial experiences of its use, some possible areas of future development are suggested. [ABSTRACT FROM AUTHOR]

Superscalar out-of-order CPU designs can achieve higher performance than simpler in-order designs through exploitation of instruction-level parallelism in software. However, these CPU designs are often considered to be unsuitable for hard real-time systems because of the difficulty of guaranteeing the worst-case execution time (WCET) of software. This paper proposes and evaluates modifications for a superscalar out-of-order CPU core to allow instruction-level parallelism to be exploited without sacrificing time predictability and support for WCET analysis. Experiments using the M5 O3 CPU simulator show that WCETs can be two-four times smaller than those obtained using an idealized in-order CPU design, as instruction-level parallelism is exploited without compromising timing safety. [ABSTRACT FROM AUTHOR]

As the software complexity drastically increases for multiresource real-time systems, industries have great needs for analytically validating real-time behaviors of their complex software systems. Possible candidates for such analytic validations are the end-to-end response time analysis techniques that can analytically find the worst-case response times of real-time transactions over multiple resources. The existing techniques, however, exhibit severe overestimation when real-time transactions visit the same resource multiple times, which we call a multiple visit problem. To address the problem, this paper proposes a novel analysis that completely changes its analysis viewpoint from classical per-job basis--aggregation of per-job response times--to per-resource basis--aggregation of per-resource total delays. Our experiments show that the proposed analysis can find significantly tighter bounds of end-to-end response times compared with the existing per-job-based analysis. [ABSTRACT FROM AUTHOR]

Estimating and optimizing worst-case execution time (WCET) is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. Recent work has shown that simple prefetching techniques such as the Next-N-Line prefetching can enhance both the average-case and worst-case performance; however, the improvement on the worst-case execution time is rather limited and inefficient. This paper studies a loop-based instruction prefetching approach, which can exploit the program control-flow information to intelligently prefetch instructions that are most likely needed. Our evaluation indicates that the loop-based instruction prefetching outperforms the Next-N-Line prefetching in both the worst-case and the average-case performance for real-time applications. [ABSTRACT FROM AUTHOR]

A systematic approach to the comparison of the graphics processor (GPU) and reconfigurable logic is defined in terms of three throughput drivers. The approach is applied to five case study algorithms, characterized by their arithmetic complexity, memory access requirements, and data dependence, and two target devices: the nVidia GeForce 7900 GTX GPU and a Xilinx Virtex-4 field programmable gate array (FPGA). Two orders of magnitude speedup, over a general-purpose processor, is observed for each device for arithmetic intensive algorithms. An FPGA is superior, over a GPU, for algorithms requiring large numbers of regular memory accesses, while the GPU is superior for algorithms with variable data reuse. In the presence of data dependence, the implementation of a customized data path in an FPGA exceeds GPU performance by up to eight times. The trends of the analysis to newer and future technologies are analyzed. [ABSTRACT FROM AUTHOR]

We propose FIT, a flexible, lightweight, and real-time scheduling system for wireless sensor platforms. There are three salient features of FIT. First, its two-tier hierarchical framework supports customizable application-specific scheduling policies, hence, FIT is very flexible. Second, FIT is lightweight in terms of minimizing the thread number to reduce preemptions and memory consumption while at the same time ensuring system schedulability. We propose a novel Minimum Thread Scheduling Policy (MTSP) exploration algorithm within FIT to achieve this goal. Finally, FIT provides a detailed real-time schedulability analysis method to help check if application's temporal requirements can be met. We implemented FIT on MicaZ motes and carried out extensive evaluations. Results demonstrate that FIT is indeed flexible and lightweight for implementing real-time applications, at the same time, the schedulability analysis provided can predict the real-time behavior. FIT is a promising scheduling system for implementing complex real-time applications in sensor networks. [ABSTRACT FROM AUTHOR]

Real-time and embedded systems have traditionally been designed for closed environments where operating conditions, input workloads, and resource availability are known a priori and are subject to little or no change at runtime. There is an increasing demand, however, for autonomous capabilities in open distributed real-time and embedded (DRE) systems that execute in environments where input workload and resource availability cannot be accurately characterized a priori. These systems can benefit from autonomic computing capabilities, such as self-(re)configuration and self-optimization, that enable autonomous adaptation under varying--even unpredictable---operational conditions. A challenging problem faced by researchers and developers in enabling autonomic computing capabilities to open DRE systems involves devising adaptive planning and resource management strategies that can meet mission objectives and end-to-end quality of service (QoS) requirements of applications. To address this challenge, this paper presents the Integrated Planning, Allocation, and Control (IPAC) framework, which provides decision-theoretic planning, dynamic resource allocation, and runtime system control to provide coordinated system adaptation and enable the autonomous operation of open DRE systems. This paper presents two contributions to research on autonomic computing for open DRE systems. First, we describe the design of IPAC and show how IPAC resolves the challenges associated with the autonomous operation of a representative open DRE system case study. Second, we empirically evaluate the planning and adaptive resource management capabilities of IPAC in the context of our case study. Our experimental results demonstrate that IPAC enables the autonomous operation of open DRE systems by performing adaptive planning and management of system resources. [ABSTRACT FROM AUTHOR]

Real-time scheduling is the theoretical basis of real-time systems engineering. Earliest Deadline First (EDF) is an optimal scheduling algorithm for uniprocessor real-time systems. Existing results on an exact schedulability test for EDF task systems with arbitrary relative deadlines need to calculate the processor demand of the task set at every absolute deadline to check if there is an overflow in a specified time interval. The resulting large number of calculations severely restricts the use of EDF in practice. In this paper, we propose new results on necessary and sufficient schedulability analysis for EDF scheduling; the new results reduce, exponentially, the calculation times, in all situations, for schedulable task sets, and in most situations, for unschedulable task sets. For example, a 16-task system that in the previous analysis had to check 858,331 points (deadlines) can, with the new analysis, be checked at just 12 points. There are no restrictions on the new results: each task can be periodic or sporadic, with relative deadline, which can be less than, equal to, or greater than its period, and task parameters can range over many orders of magnitude. [ABSTRACT FROM AUTHOR]