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The four-quadrant analog multipliers (FQAM) are widely used in signal processing applications such as amplitude modulation, frequency doubling, and adaptive filters. In this paper, a FQAM has been realised in dynamic threshold voltage MOSFET (DTMOS) technology. It relies on the square-law characteristics of the MOS transistor. Several simulations have been carried out to assess the operation of the proposed FQAM. The supply voltage is set to ±0.2 V, and 68 µW power consumption is determined. The input signal can be applied to the full scale of the supply voltage. The bandwidth is 22.86 MHz, and the output signal's total harmonic distortion (THD) is less than 2%. Intermodulation products of the output signal have been calculated. Monte Carlo and temperature simulations have been performed in a way that confirms the robustness of the circuit against the technological spread. In summary, low power consumption, wide bandwidth, and linearity are the advantages of the proposed circuit. [ABSTRACT FROM AUTHOR]

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18 μ m TSMC (level-49) CMOS technology. Simulation results with ± 0. 7 -V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the − 3 dB bandwidth (BW) is 903 MHz, the total harmonic distortion (THD) is 0.3% (at 1 MHz), and the maximum and static power consumption are 1 3 9. 2 5 μ W and 1 4. 5 μ W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the − 3 dB BW as 657 MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work's performance. [ABSTRACT FROM AUTHOR]

Combined radial–axial magnetic bearings (MBs) use a common bias magnetic circuit to provide radial and axial bias magnetic flux. Different from separate MBs, there is a constraint relation between the radial and axial bias flux. Meanwhile, there is also a constraint relationship between the radial and axial maximum bearing capacity. Therefore, the design method for separated MB is not suitable for a combined radial‐axial MB (CRAMB). In this study, a design method of the CRAMB based on an asymmetric factor was proposed. The definition of the asymmetric factor was proposed. In order to avoid the radial and axial magnetic flux into the weak magnetic field and saturation region, the optimum range of the asymmetric factor is analysed. The influence of the asymmetry factor on stiffness is analysed; the prototype designed by this method can run stably. The validity and accuracy of the design method are verified by experimental results. [ABSTRACT FROM AUTHOR]

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the − 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered. [ABSTRACT FROM AUTHOR]

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Copyright of Chinese Journal of Liquid Crystal & Displays is the property of Chinese Journal of Liquid Crystal & Displays and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A highly linear and efficient CMOS power amplifier (PA) with adaptive auxiliary amplifier control (AAAC) is presented, which makes the common‐gate transistor of an auxiliary amplifier operate in the saturation region for overall output powers. This leads to decrease the AM–PM distortion by reducing the variation of the output susceptance. In addition, the AAAC reduces the current consumption for all power ranges by controlling the auxiliary amplifier. The PA is fully integrated with all matching networks in a 0.18 μm CMOS process. It was measured with an 802.11n 64‐QAM MCS7 signal. It achieved a maximum average power of 19.9 dBm with a power‐added efficiency of 28% under an error‐vector magnitude of −25 dB. [ABSTRACT FROM AUTHOR]

A computationally efficient simulation model for the drain current characteristics of long-channel amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is developed. This model uses numerical solutions of the one-dimensional Poisson equation to significantly reduce the calculation time compared to a widely used two-dimensional approach. Moreover, for accurate simulation, the model takes into account the influence of trap states in the band gap, which makes it possible to reproduce the gradual increase of the drain current in the subthreshold region. The model also includes both drift and diffusion components of the drain current and so can describe the drain current in all regions of device operation, i.e., the subthreshold, linear, and saturation regions, by using a unified current equation without introducing the threshold voltage as an input parameter. Calculations using the model provide results that are in good agreement with the measured drain current characteristics of a-IGZO TFTs over a wide range of gate and drain voltages. The presented model is expected to enable faster and accurate characteristic analysis and structure design for a-IGZO TFTs. [ABSTRACT FROM PUBLISHER]

This paper proposes technique for mitigating an issue of 'reduced signal voltage range' in existing analog signal processing circuits in finer technologies due to their low supply voltage. The proposed adaptively-biased MOSFET pair can make an MOSFET operate in the saturation or the triode region in a wider voltage range. The simulated results of a source-coupled pair with the proposed structure by using Cadence Spectre and MOSFET parameter of a 0.18 μm CMOS technology are also presented. [ABSTRACT FROM AUTHOR]

In this paper, a class of delayed cellular neural networks with unbounded activation functions and described by using space invariant cloning templates are considered. The general and explicit existing regions of equilibrium points are discussed based on dissipative theory, fixed point principle of iteration mapping and Brouwer Fixed-point Theorem. The sufficient condition is obtained to ensure the existence, uniqueness, local asymptotical stability of the equilibrium point in each saturation sub-region. Moreover, we give the condition for equilibrium point to be globally exponentially stable, and the explicit existing region of the unique equilibrium point is also located. These results extend previous works on these issues for the standard delayed cellular neural networks. Two numerical examples are given to show the validity of the obtained results. [ABSTRACT FROM AUTHOR]

This paper discusses the issues of current flow in the diode structures with an oxide cathode. Have been analyzed of theoretical and experimental anode characteristics of cylindrical diodes with a split anode. It is shown that in the range of anode voltage greater than the maximum observed effect of spontaneous growth of the anode current and increases the discrepancy between theoretical and experimental characteristics of diode structures. It was established that at this voltage occurs electron-stimulated desorption of ions from the anode surface with subsequent bombardment of the cathode, which causes secondary electron emission and additional growth of the anode current. This process is accompanied by a considerable increase in the temperature of the anode due to electron bombardment of the surface. [ABSTRACT FROM AUTHOR]

A new method is presented for extracting Taylor series coefficients directly from IM measurements for modeling IM distortion in HEMT and MESFET circuits. It is based on an improved model that uses better simplifying assumptions. The method gives a substantially more accurate characterization, especially in the saturation region, required for amplifier designs [ABSTRACT FROM PUBLISHER]