Search

In this study, titanium nitride (TiN) is synthesized using reactive sputtering for a self-aligned gate process. The Schottky barrier height of the TiN on n-GaN is around 0.5 to 0.6 eV and remains virtually constant with varying nitrogen ratios. As compared with the conventional Ni electrode, the TiN electrode presents a lower turn-on voltage, while its reverse leakage current is comparable with that of Ni. The results of annealing evaluation at different temperatures and duration times show that the TiN/W/Au gate stack can withstand the ohmic annealing process at 800°C for 1 or 3 min. Finally, the self-aligned TiN-gated AlGaN/GaN heterostructure field-effect transistors are obtained with good pinch-off characteristics. [ABSTRACT FROM AUTHOR]

We propose a thermal sensor using poly-Si thin-film transistors (TFTs) with self-aligned and offset gate structures. First, the temperature dependences of the transistor characteristic are compared between the self-aligned and offset TFTs. It is found that both the TFTs have the temperature dependence of the off-leakage current, whereas the off-leakage current of the self-aligned TFT is larger than that of the offset TFT. Next, the self-aligned and offset TFTs are included in a cell circuit to detect the temperature utilizing the off-leakage current, which is composed of a pair of 1-transistor and 1-capacitor. It is found that low and high temperatures can be detected using the self-aligned and offset TFTs, respectively. We think that it is promising to integrate this thermal sensor in certain applications using TFTs. [ABSTRACT FROM PUBLISHER]

Continued research into the development of III–V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and ‘standard’ T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system. [ABSTRACT FROM AUTHOR]

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower OFF-state current (177 to 6.29 nA), and the ON/OFF current ratio is only slightly decreased from 1.71 × 107 to 1.39 × 107. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications. [ABSTRACT FROM AUTHOR]