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A Ku band frequency synthesizer is designed and implemented in 0.13μm SiGe technology as a part of an E-band superhetrodyne transceiver chipset. It provides for RF channels of 71–76 GHz in 62.5MHz steps, and features a phase rotating pulse injection division region switching subinteger frequency divider. Output frequency ranges from 15.4 to 16.7 GHz. The measured differential output power is about −6 dBm measured phase noise at 100-kHz 1-MHz and 10MHz is −84, −111 and −131 dBc/Hz, respectively. Reference spurs are at −44 dBc and sub-integer spurs are at −45dBc, with power consumption of 166mW. [ABSTRACT FROM PUBLISHER]

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71–76GHz and upper 81–86GHz bands were designed and fabricated in 0.13µm SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve maximum gain of 65dB, 6dB noise figure, better than −10 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 17.5 to 18.5 dBm, Psat of 20.5 to 21.5 dBm, an analog controlled dynamic range of 30 dB and consumes 1.75 W. [ABSTRACT FROM PUBLISHER]

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71–76GHz and upper 81–86GHz bands were designed and fabricated in 0.13%m SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve 60dB gain, 8.5 dB noise figure, −30 dBm IIP3, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency multiplier by four (quadrupler). It achieves output power P1dB of 0 to 11 dBm, Psat of 3.3 to 14 dBm, and consumes 850 mW. [ABSTRACT FROM PUBLISHER]

This paper presents a fully integrated 71–76GHz power amplifiers (PA) fabricated in a 0.12µm SiGe BiCMOS technology. The PA employs five common-emitter stages with on-chip power combining to achieve power gain of 21dB, 17.6dBm output power at 1dB compression, and saturated power of 20.1dBm. The modified Wilkinson combiner that was used shows 0.5dB insertion loss. Small signal characteristics of the amplifier show peak gain at 72GHz with 3dB bandwidth of 17GHz (24%). The PA's bias is applied using digitally adjustable PTAT bias circuits and it consumes quiescent currents of 140mA from a 2V supply and 280mA at 1dB compression. [ABSTRACT FROM PUBLISHER]