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A new multiple orientation event-based neurobiological recognition system is proposed by integrating recognition and tracking function in this paper, which is used for asynchronous address-event representation (AER) image sensors. The characteristic of this system has been enriched to recognize the objects in multiple orientations with only training samples moving in a single orientation. The system extracts multi-scale and multi-orientation line features inspired by models of the primate visual cortex. An orientation detector based on modified Gaussian blob tracking algorithm is introduced for object tracking and orientation detection. The orientation detector and feature extraction block work in simultaneous mode, without any increase in categorization time. An addresses lookup table (addresses LUT) is also presented to adjust the feature maps by addresses mapping and reordering, and they are categorized in the trained spiking neural network. This recognition system is evaluated with the MNIST dataset which have played important roles in the development of computer vision, and the accuracy is increased owing to the use of both ON and OFF events. AER data acquired by a dynamic vision senses (DVS) are also tested on the system, such as moving digits, pokers, and vehicles. The experimental results show that the proposed system can realize event-based multi-orientation recognition. The work presented in this paper makes a number of contributions to the event-based vision processing system for multi-orientation object recognition. It develops a new tracking-recognition architecture to feedforward categorization system and an address reorder approach to classify multi-orientation objects using event-based data. It provides a new way to recognize multiple orientation objects with only samples in single orientation. [ABSTRACT FROM AUTHOR]

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 x 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 µm CMOS process. The proposed ADC has average power consumption of 128 µW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors. [ABSTRACT FROM AUTHOR]

In system level design or architecture design stage of SoCs, it is important to estimate the system parameters such as bus utilization and buffer capacity. A novel bus modeling method which was derived from Markov model for obtaining these parameters of an on-chip-bus system has been proposed in this paper. This modeling approach employs Markov chain to describe the state change of the system. This method was used in architecture design verification of a video format converting (VFC) chip. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method were verified, and more than 55% of FIFOs size are saved. It is suitable for analyzing various bus systems, such as user-defined buses, industrial standard buses, multi-core and multi-bus systems. [ABSTRACT FROM AUTHOR]

A current source circuit for high-resolution CMOS image sensors is introduced in this paper, which can provide a stable current with immunity from IR-drop along the power and ground wires. In the circuit, two pre-charged floating capacitors controlled by two-phase non-overlap clock are connected between the gate and source of a MOS transistor alternately to maintain a constant VGS of the MOS transistor. In this way, the current flowing through the MOS transistor will be stable and has nothing to do with power level. The post simulation results show that the current supplied by the proposed circuit decreases only by 1.6% when the voltage of the power supply decreases by 30%. The simulations have proved that the proposed circuit can improve the performance of high-resolution CMOS image sensors. [ABSTRACT FROM AUTHOR]

As technology scales, the protection of Finite State Machines' (FSMs) states against single event upset (SEU) and multiple bit upsets (MBUs) becomes more difficult. In this paper, a self-checking approach to enhance the SEU/MBUs immunity of FSMs' states by replicating One-Hot code M times for state encoding is presented. This approach can correct less than M bit-flip faults in the state register per cycle. Bit-flips are treated as random events and modeled by applying Poisson distribution. Two characteristics of this approach are obtained through probability analysis: first, this approach performs better with the increase of M, whereas worse when an FSM contains more states; second, this approach can offer more enhanced reliability than Binary or One-Hot state encoding with Triple Modular Redundancy (TMR). The former characteristic leads to the further improvement of this approach which is called state-reforming. The reliabilities of this proposed approach and its state-reformed solutions, as well as One \mathchar"702D Hot +TMR are all evaluated through simulations of fault injections. [ABSTRACT FROM PUBLISHER]

With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored. [ABSTRACT FROM PUBLISHER]

On the basis of n-type single-crystal (100) silicon substrate, a silicon p-n junction photodetector has been successfully developed. Three methods to improve photoresponse signal-to-noise ratio (SNR) were profoundly studied: the p-n junction depth was optimized to enhance the spectral responsivity within the wavelength range of 500-600 nm, an antireflection layer with the appropriate thickness was added to reduce the reflected light and enhance the sensitivity, the adjustment technique of spectral band response was adopted to remove the noise signal with normal silicon absorptive wavelengths. Eventually, the spectral responsivity SNR can be over 104 at 500-600 nm while the peak of spectral responsivity is 0.48 A/W at about 520 nm. After being optimized, silicon p-n junction photodetectors, which possess the properties of lower dark current, higher sensitivity, shorter response time and larger SNR, can be achieved. [ABSTRACT FROM AUTHOR]