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A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs. [ABSTRACT FROM AUTHOR]

Crystalline materials with broken inversion symmetry can exhibit a spontaneous electric polarization, which originates from a microscopic electric dipole moment. Long-range polar or anti-polar order of such permanent dipoles gives rise to ferroelectricity or antiferroelectricity, respectively. However, the recently discovered antiferroelectrics of fluorite structure (HfO2 and ZrO2) are different: A non-polar phase transforms into a polar phase by spontaneous inversion symmetry breaking upon the application of an electric field. Here, we show that this structural transition in antiferroelectric ZrO2 gives rise to a negative capacitance, which is promising for overcoming the fundamental limits of energy efficiency in electronics. Our findings provide insight into the thermodynamically forbidden region of the antiferroelectric transition in ZrO2 and extend the concept of negative capacitance beyond ferroelectricity. This shows that negative capacitance is a more general phenomenon than previously thought and can be expected in a much broader range of materials exhibiting structural phase transitions. Applying an electric field to an antiferroelectric material transforms its non-polar crystal structure into a polar one. Here, the authors show that the antiferroelectric transition in zirconia causes a negative capacitance, useful for electronics. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (FEFETs) are an important candidate for emerging nonvolatile memory applications but suffer from a lack of physical understanding of the device operation. Previous FEFET models utilized the Preisach model of ferroelectrics and do not accurately capture the physics of the FEFET that the majority of the polarization charge is screened by trapped charge at the interfaces. We propose an empirical model for FEFETs, which also considers screening of ferroelectric polarization. The screening charge is modeled as a dissipative (leakage) current across the baseline MOS gate-stack. The proposed model is calibrated using the experimental data of p-type ZrO2 FEFETs and unravels the weak electrostatic coupling between the ferroelectric polarization and semiconductor channel charge. In addition, the model captures the memory window discrepancy between the charge–voltage characteristics and current–voltage characteristics observed in the experimental data, provides new insight into the ferroelectric device, and is well-suited for use as a compact model implementation of FEFETs. [ABSTRACT FROM AUTHOR]

While the theoretical maximum of the memory window $\Delta {V}_{t}$ in a ferroelectric field-effect transistor (FEFET) is $2{E}_{C}{t}_{F}$ , ${E}_{C}$ and ${t}_{F}$ being coercive field and FE thickness, respectively, experimentally $\Delta {V}_{t}$ is observed to be much less than that, even in the case of complete polarization switching in the ferroelectric layer. This occurs because trapped charges in the gate oxide stack partially or completely screen the ferroelectric polarization, only a fraction of which gets “electrostatically” reflected in the semiconductor channel. In this article, we provide a generalized experimental framework to quantify the efficiency of practical FEFETs in converting the switched ferroelectric polarization into the memory window. To that end, we propose three efficiency metrics: 1) switched ferroelectric polarization $\Delta {P}_{F}$ to memory window conversion ratio, $\eta _{MW}=\Delta {V}_{t}/\Delta {P}_{F}$ ; 2) switched ferroelectric polarization to the semiconductor charge ($\Delta {Q}_{S}$) conversion efficiency or the charge conversion efficiency $\eta _{c}=\Delta {Q}_{s}/\Delta {P}_{F}$ ; and 3) the ratio of memory window to the width of polarization versus gate voltage hysteresis characteristics ($\Delta {V}_{P}$) or the voltage conversation efficiency $\eta _{V}=\Delta {V}_{t}/\Delta {V}_{P}$. We measure and compare these efficiency metrics in n-type and p-type FEFETs, fabricated in different facilities by different groups. In all the cases, we find that the maximum values of memory window efficiency $(\eta _{MW})_{max}$ , charge conversion efficiency $(\eta _{c}$) $_{max}$ , and voltage conversion efficiency ($\eta _{V}$) $_{max}$ are in the range: 2.5–5.5 Vm2/C, 4%–10%, and 5%–20%, respectively. [ABSTRACT FROM AUTHOR]

Originally based on phenomenological observations, the Janovec–Kay–Dunn (JKD) scaling law has been historically used to describe the dependence of the ferroelectric coercive fields (Ec) on a critical length scale of the material, wherein the film thickness (t) is considered the length scale, and Ec ∝ t−2/3. Here, for the first time, a JKD‐type scaling behavior is reported in an antiferroelectric material, using the ultra‐thin films of prototypical flourite‐structure binary oxide, zirconia. In these films, a decrease in the ZrO2 layer thickness from 20 nm to 5.4 nm leads to an increase in critical fields for both nonpolar‐to‐polar (Ea), and polar‐to‐nonpolar (Ef) transitions, accompanied by a decrease in the average crystallite size, and an increase in the tetragonal distortion of the non‐polar P42/nmc ground state structure. Notably, the ‐2/3 power law as in the JKD law holds when average crystallite size (d), measured from glancing‐incident X‐ray diffraction, is considered as the critical length scale—i.e., Ea, Ef ∝ d−2/3. First principles calculations suggest that the increase of tetragonality in thinner films contributes to an increase of the energy barrier for the transition from the non‐polar tetragonal ground state to the field‐induced polar orthorhombic phase, and in turn, an increase in Ea critical fields. These results suggest a de‐stabilization of the ferroelectric phase with a decreasing thickness in antiferroelectric ZrO2, which is contrary to the observations in its fluorite‐structure ferroelectric counterparts. With the recent interests in utilizing antiferroelectricity for advanced semiconductor applications, our fundamental exposition of the thickness dependence of functional responses therein can accelerate the development of miniaturized, antiferroelectric electronic memory elements for the complementary metal‐oxide‐semiconductor based high‐volume manufacturing platforms. [ABSTRACT FROM AUTHOR]

Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) $ZrO_{2}$ based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses ($t_{FE}$ and $t_{IL}$ , respectively) on device performance. We observe that a decrease of $t_{FE}$ and $t_{IL}$ reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of $t_{FE}$ , $t_{IL}$ and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - notwithstanding the fact that the reliability implications of the magnitude of FE polarization still need to be understood. [ABSTRACT FROM AUTHOR]

To scale the ferroelectric random access memory (FeRAM) technology toward 28 nm or beyond, it is critical to develop stacked capacitor (with sufficient surface area) to allow good sense margin for the 1-transistor- 1-capacitor (1T1C) bit cell. Therefore, to enable 3-D integration in back-end-of-line (BEOL) process, it is essential to optimize the fabrication recipes in low-thermal budget (< 400 °C). In this regard, we investigated the low-temperature process for ferroelectric Hf0.5Zr0.5O2 (HZO) capacitor with the plasma-enhanced atomic layer deposition (PEALD). It was found that, with sufficient annealing time (>50 s) in low temperature (~ 350 °C), the ferroelectric properties of HZO could be fully manifested. No degradation is shown in the remnant polarization (Pr) under the optimized low-temperature process. Furthermore, the retention/endurance characteristics with different Pr states were measured to determine the minimally required write voltage. Finally, the SPICE simulation is conducted to evaluate the sense margin of the projected 28-nm 1T1C array with stacked cylindrical capacitors using the measured Pr drift behavior over time. [ABSTRACT FROM AUTHOR]

Flourite-structure ferroelectrics (FEs) and antiferroelectrics (AFEs) such as HfO2 and its variants have gained copious attention from the semiconductor community, because they enable complementary metal-oxide-semiconductor (CMOS)-compatible platforms for high-density, high-performance non-volatile and volatile memory technologies. While many individual experiments have been conducted to characterize and understand fluorite-structure FEs and AFEs, there has been little effort to aggregate the information needed to benchmark and provide insights into their properties. We present a fast and robust modeling framework that automatically fits the Preisach model to the experimental polarization ( Q FE ) versus electric field ( E FE ) hysteresis characterizations of fluorite-structure FEs. The modifications to the original Preisach model allow the double hysteresis loops in fluorite-structure antiferroelectrics to be captured as well. By fitting the measured data reported in the literature, we observe that ferroelectric polarization and dielectric constant decrease as the coercive field rises in general. [ABSTRACT FROM AUTHOR]

A ferroelectric material in a ferroelectric–dielectric heterostructure can provide a charge boost, as often discussed in the context of negative capacitance, and, in doing so, can reduce the power dissipation in field-effect transistor technology. However, there is an ongoing debate on whether the charge boost in such a heterostructure is a transient phenomenon or a steady state one. In this Letter, we use the positive-up-negative-down (PUND) measurement technique on a ferroelectric–dielectric (FE–DE) capacitor to show that the charge boost is a steady-state effect—i.e., the charge boost remains intact after the initial transient effects subside and all the voltages in the system reach constant values and steady states. We also demonstrate differential charge boost in steady state using a staircase voltage pulse measurement technique. An experimentally calibrated multi-domain SPICE model of an FE–DE stack is used to accurately simulate the PUND and staircase voltage hopping methods. [ABSTRACT FROM AUTHOR]

Since the discovery of ferroelectricity in doped/alloyed HfO2 and ZrO2 thin film, many device engineers have been attracted to its sustainable ferroelectricity at the thickness of a few nanometer. While most of the previous studies have mainly focused on the ferroelectric properties of the thermally atomic layer deposited (THALD) Hf0.5Zr0.5O2 (HZO), the plasma-enhanced ALD (PEALD) HZO has not received much attention. In this work, a direct comparison between the two types of HZO thin films is carried out, where we found that a tradeoff exists between these two fabrication methods. While the THALD HZO was able to maintain a higher cycling endurance, the PEALD HZO showed more stable characteristics over the cycling with reduced wake-up and fatigue effects, in addition to better tolerance against breakdown under high electric field. Furthermore, the PEALD HZO could be crystallized with post deposition annealing at 350 °C, which is of great interest for the back-end-of-line compatibility with silicon fabrication processes. [ABSTRACT FROM AUTHOR]

We report the effects of lanthanum doping/alloying on antiferroelectric (AFE) properties of ZrO2. Starting with pure ZrO2, an increase in La doping leads to the narrowing of the AFE double hysteresis loops and an increase in the critical voltage/electric field for AFE → ferroelectric transition. At higher La contents, the polarization-voltage characteristics of doped/alloyed ZrO2 resemble that of a non-linear dielectric without any discernible AFE-type hysteresis. X-ray diffraction based analysis indicates that the increased La content while preserving the non-polar, parent AFE, tetragonal P42/nmc phase leads to a decrease in tetragonality and the (nano-)crystallite size and an increase in the unit cell volume. Furthermore, antiferroelectric behavior is obtained in the as-deposited thin films without requiring any capping metallic layers and post-deposition/-metallization anneals due to which our specific atomic layer deposition system configuration crystallizes and stabilizes the AFE tetragonal phase during growth. [ABSTRACT FROM AUTHOR]

B Ultra-High Density Memory b Antiferroelectric oxides are a promising candidate for next-generation, ultra-high density memory technologies. In article 2100485, Nazanin Bassiri-Gharb, Asif Islam Khan, and colleagues show that the critical polar - antipolar transition voltages in prototypical fluorite-structured antiferroelectric ZrO SB 2 sb thin films show a -2/3 power law dependence on the average crystallite size, in analogy to the Janovec-Kay-Dunn Law for ferroelectrics. A Janovec-Kay-Dunn-Like Behavior at Thickness Scaling in Ultra-Thin Antiferroelectric ZrO2 Films (Adv. [Extracted from the article]