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Silicon nitride films are widely used as the charge storage layer of charge trap flash (CTF) devices due to their high charge trap densities. The nature of the charge trapping sites in these materials responsible for the memory effect in CTF devices is still unclear. Most prominently, the Si dangling bond or K-center has been identified as an amphoteric trap center. Nevertheless, experiments have shown that these dangling bonds only make up a small portion of the total density of electrical active defects, motivating the search for other charge trapping sites. Here, we use a machine-learned force field to create model structures of amorphous Si 3 N 4 by simulating a melt-and-quench procedure with a molecular dynamics algorithm. Subsequently, we employ density functional theory in conjunction with a hybrid functional to investigate the structural properties and electronic states of our model structures. We show that electrons and holes can localize near over- and under-coordinated atoms, thereby introducing defect states in the band gap after structural relaxation. We analyze these trapping sites within a nonradiative multi-phonon model by calculating relaxation energies and thermodynamic charge transition levels. The resulting defect parameters are used to model the potential energy curves of the defect systems in different charge states and to extract the classical energy barrier for charge transfer. The high energy barriers for charge emission compared to the vanishing barriers for charge capture at the defect sites show that intrinsic electron traps can contribute to the memory effect in charge trap flash devices. [ABSTRACT FROM AUTHOR]

Leakage currents through dielectrics in modern logic, memory, and power devices, and back-end interlevel layers can severely increase the time-zero power dissipation and shorten the lifetime of the material structure. Depending on thickness, material properties, and fabrication quality, different conduction mechanisms through the insulating layer, such as band-to-band and trap-assisted tunneling (TAT) are observed. These leakage currents can be distinguished by their dependence on electric field strength, temperature, and their transient characteristics. The identification of the underlying mechanisms is of utmost importance for the selection of suitable dielectrics and optimization of device processing. In this work, we present a nonradiative multiphonon model which extends our compact physics (Comphy) reliability framework to also account for TAT. The model is based on a single physical defect parameter set from which charge transfer kinetics between charge carrier reservoirs and oxide defects (single-TAT) as well as between the defects (multi-TAT) can be derived. We thereby demonstrate that the thermal barrier for inelastic defect–defect carrier tunneling is approximately twice as large in comparison to reservoir-defect interaction and further show in which parameter regime multi-TAT plays a role. Our results show that multi-TAT currents are a less important contribution to the overall tunnel current than previously assumed. [ABSTRACT FROM AUTHOR]

Using the framework developed in the first part of this work, we demonstrate the capabilities of the extended two-state nonradiative multi-phonon (NMP) model by reproducing leakage current characteristics of two selected technologies. First, we identify the temperature-activated leakage mechanism in SiC / SiO2 stacks using a tens of nanometer thick thermally grown oxide as trap-assisted tunneling (TAT) through defects. Interestingly, this effect can be reproduced with the same parameters in a SiC / SiO2 stack with deposited oxide. Our simulations demonstrate that these charge transition centers are distributed within only a few nanometers from the SiC / SiO2 interface. The low thermal activation of the leakage current is linked to the low relaxation energies of the involved traps compared with those typically involved in bias temperature instability (BTI) and Random Telegraph Noise (RTN). Second, a similar mechanism can explain TAT characteristics and transient charge trapping currents in Metal–Insulator–Metal (MIM) capacitors with a ZrO2 insulating layer. By comparison of our model parameters to theoretical density functional theory (DFT) calculations, we identify self-trapped electrons (polarons) as a likely cause for these effects, as they have the required low relaxation energies. [ABSTRACT FROM AUTHOR]

We investigate the temperature dependence of the hysteresis in the transfer characteristics of 4H silicon carbide (4H-SiC) lateral MOSFETs. Within temperatures ranging from 150 to 300 K, we experimentally characterize the hysteresis width as the difference of the threshold voltage between up and down sweeps. We observe a considerable increase in the hysteresis width toward lower temperatures. When the gate voltage sweeps up, the threshold voltage shifts toward positive gate voltages. This shift is maintained even during the subsequent down sweep. We attribute this behavior to acceptor-like border traps, which get more negatively charged at higher gate voltages. These traps are presumably located near the SiC/SiO2 interface with energy levels close to the SiC conduction band edge. Using a two-state non-radiative multi-phonon model, we calculated capture and emission times to show that the hysteresis width corresponds to the charge stored on these traps and, hence, possesses an intrinsic temperature dependence due to the transition barriers. [ABSTRACT FROM AUTHOR]

CMOS circuits based on scaled transistors are typically more susceptible to soft errors caused by energetic particles in the radiation environment than circuits employing their large-area counterparts. In this paper, a soft error tolerant latch built on a Schmitt trigger, which is entirely realized with NMOS transistors with an additional voltage booster, which we refer to as NST-VB, is proposed. To evaluate the circuits' radiation resilience, we identify the most sensitive nodes by analyzing the critical charges at the various latches' internal sensitive nodes. We also examine the linear energy transfer (LET) of the essential latches and observe that the NST-VB latch has an improved LET of 0.386 MeV cm 2 / mg as compared to 0.231 MeV cm 2 / mg and 0.365 MeV cm 2 / mg for unhardened latch and ST latch, respectively. For the process variation analysis, we further examined 5k Monte Carlo simulations to analyze the impact of device variability on our design and observe that the proposed NST-VB latch has 1.96 × less variability critical voltage concerning the ST latch. Further, the logic flipping probability for NST-VB latch is 48.32% compared to 53.04% for ST latch. Also, the critical charge to power delay area product ratio (QPAR) is calculated and evaluated for the proposed latch's effectiveness compared to other considered latches. [ABSTRACT FROM AUTHOR]

Charge trapping is arguably the most important detrimental mechanism distorting the ideal characteristics of MOS transistors, and nonradiative multiphonon (NMP) models have been demonstrated to provide a very accurate description. For the calculation of the NMP rates at room temperature or above, simple semiclassical approximations have been successfully used to describe this intricate mechanism. However, for the computation of charge transition rates at cryogenic temperatures, it is necessary to use the full quantum mechanical description based on Fermi’s golden rule. Since this is computationally expensive and often not feasible, we discuss an efficient method based on the Wentzel–Kramers–Brillouin (WKB) approximation in combination with the saddle point method and benchmark this approximation against the full model. We show that the approximation delivers excellent results and can, hence, be used to model charge trapping behavior at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

We present time-zero characterization and an investigation on bias temperature instability (BTI) degradation between 4 and 300 K on large area high- ${k}$ CMOS devices. Our measurements show that negative BTI (NBTI) on pMOSFETs freezes out when approaching cryogenic temperatures, whereas there is still significant positive BTI (PBTI) degradation in nMOSFETs even at 4 K. To explain this behavior, we use an efficient implementation of the quantum mechanical nonradiative multiphonon charge trapping model presented in Part I and extract two separate trap bands in the SiO2 and HfO2 layer. We show that NBTI is dominated by defects in the SiO2 layer, whereas PBTI arises mainly from defects in the HfO2 layer, which are weakly recoverable and do not freeze out at low temperatures due to dominant nuclear tunneling at the defect site. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) MOSFETs still exhibit higher drifts of the threshold voltage than comparable silicon devices due to charge trapping, especially regarding small time scales. Understanding this behavior and the consequences in application relevant conditions is therefore of high research interest. Since charge trapping at different defects close to the SiC/ SiO2 interface and in the bulk oxide is strong bias and temperature-dependent, the phenomenon is referred to as bias temperature instability (BTI). It has been shown that drifts caused by BTI vary both in transient shape and magnitude for commercially available devices. These differences arise from defect densities and properties in the respective technologies. A physical model together with defect parameters that explain the charge transfer reactions at the defects is essential to understand all peculiarities of the transient degradation. In this work, we use a novel method to semiautomatically extract defect parameters within a two-state nonradiative multiphonon model framework. Our work reveals properties of defects responsible for shifts of the threshold voltage for both short-term ac and long-term dc stress conditions which are accurately reproduced for three different DMOS technologies. Our calibrated simulation framework is further used to extrapolate device degradation at operation relevant ac bias conditions to typical device lifetimes. [ABSTRACT FROM AUTHOR]

Defects in the gate oxide give rise to bias temperature instability (BTI), which is considered a serious threat to the device reliability of ultrascaled MOSFETs. Extrapolating the device degradation over the operational lifetime, therefore, requires detailed knowledge about the distributions of defects causing BTI. Typically, BTI degradation is modeled by calibrating a predefined defect parameter distribution, such as normally distributed defect bands, by employing measure-stress-measure (MSM) sequences at various temperatures. Here, we present the Effective Single Defect Decomposition (ESiD), a novel method for a semiautomated extraction of defect parameters from MSM experiments which does not require any prior assumptions about their distributions. This technique decomposes the MSM sequences into contributions from dominant effective single-defects and constructs a defect parameter distribution that reproduces the experimental data with high accuracy. We validate this new method by comparing its results to density functional theory (DFT) predictions and single-defect characterizations. [ABSTRACT FROM AUTHOR]

Altering the performance of single transistors and integrated circuits at nominal operating conditions over time, as well as soft errors, are serious reliability issues for integrated CMOS circuits, especially when used in space applications. In principle, the effect of soft errors becomes even more critical if the circuit performance degrades over time. To address this detrimental behavior, the impact of performance degradation due to NBTI on the soft error susceptibility of integrated circuits is analyzed thoroughly. For this, we analyze the critical charge sensitivity of the two‐input NAND gate and NOR gate for different operating temperatures at stress times up to 3 years. The results show that the critical charge decreases with the temperature and strongly depends on the input states. Next, we validate the results employing the c17 ISCAS'85 benchmark suite, employing the PTM model with the HSPICE to estimate the soft error at the sensitive nodes. The critical charge is observed to be sensitive to the selected supply voltage and device temperature and thus provides a good measure for the soft error susceptibility with respect to NBTI at various operation conditions. [ABSTRACT FROM AUTHOR]

Characterizing mixed hot-carrier/bias temperature instability (BTI) degradation in full VG, VDbias space is a challenging task. Therefore, studies usually focus on individual degradation mechanisms, such as BTI and hot-carrier degradation (HCD). However, a simple superposition of these mechanisms at an arbitrary VG, VD combination often fails to predict the cumulative damage. We experimentally acquired a large data set covering the full bias space of a pMOSFET which allows us to obtain detailed degradation and recovery maps. Our models for describing oxide and interface defects provide physical insights into the underlying mechanisms and a possible interplay between the degradation modes. Additionally, we perform a dedicated experiment to reveal the implications of different stress regimes onto the various types of defects by switching BTI and HCD stress conditions. The results clearly reveal the conceptual limits of the assumption of independent degradation regimes. [ABSTRACT FROM AUTHOR]

It is commonly accepted that the performance and time-to-failure of modern semiconductor transistors are seriously affected by single defects located in the insulator or at the insulator/semiconductor interface. The impact of such single defects on the device current ranges from several pico-ampere up to hundreds of nano-ampere and their characterization poses a major challenge for measurement instruments. However, for an accurate description of the device behavior under operation, the understanding of the physical mechanism behind single-charge trapping is inevitable. For this a large variety of defects and devices with different geometries have to be studied. However, the impact of single defects on the device current rapidly decreases with increasing effective gate area. Thus, suitable measurement instruments have to provide a high current measurement resolution at a large signal-to-noise ratio (SNR) for monitoring single charge transitions. To enable defect spectroscopy at a very detailed level an ultra-low noise defect probing instrument (DPI) is invented. The compact implementation and optional usage of a lead battery supply unit for the DPI guarantees highest SNR and also long-term stability over more than two years, which is typically hard to achieve when instruments of different manufacturers are connected. Utilizing the DPI a measurement resolution of a few micro-volts in terms of threshold voltage shift can be achieved, which fairly outweighs the results obtained with general-purpose instruments. [ABSTRACT FROM AUTHOR]

In modern MOS technologies continuous scaling of the geometry of transistors has led to an increase of the variability between nominally identical devices. To study the variability and reliability of such devices, a statistically significant number of samples needs to be tested. In this work we present a characterization study of defects causing BTI and RTN, performed on custom built arrays consisting of thousands of nanoscale devices. In such nanoscale devices, variability and reliability issues are typically analyzed for individual defects. However, the large number of measurements needed to extract statistically meaningful results make this approach infeasible. To analyze the large set of measurement data, we employ statistical distributions of the threshold voltage shifts arising from defects that capture and emit charge. This allows us to extract defect statistics using a defect-centric approach. Defect distributions are characterized for various gate, drain and bulk biases, and for two geometries to verify the methodology and to obtain statistics suitable for TCAD modeling and lifetime estimation. With the TCAD models we extrapolate the observed degradation of the devices. Finally, we investigate the influence of bulk and drain stress biases on the defects and observe that the impact of bulk bias on the device degradation is similar to that of the gate bias. In contrast, drain stress with drain biases up to −0.45V appears to be negligible for the investigated technology. Our measurements also clearly reveal that the overall BTI degradation is heavily dependent on the gate-bulk stress bias, while the extracted number of RTN defects seems to be independent on stress. [ABSTRACT FROM AUTHOR]

In this paper, we examine the interplay of two serious reliability issues in MOSFET devices, namely, bias temperature instability (BTI) and hot-carrier degradation (HCD). Most publications are devoted to the characterization of either BTI or HCD, and complex models have been developed to independently describe each degradation mode. However, very limited data are available on the interplay of both degradation regimes, particularly the effect of a drain bias onto the charging and discharging dynamics of oxide traps. Part I of this paper provides an extensive experimental study toward the impact of mixed-mode stress conditions on the dynamics of oxide defects. Here, we present the first microscopic modeling approach beyond a simple electrostatic approximation. We extend the existing nonradiative multiphonon theory by taking nonequilibrium processes such as full carrier distribution functions which include the effect impact ionization along the channel into account. To ultimately validate our framework, we compare simulation results and experimental data for a single-oxide defect as well as a large ensemble of traps in a MOSFET device. We show that our modeling approach accurately captures the rather puzzling measurement trends for a broad stress regime and allows developing the knowledge on how oxide defects can be affected by an increased drain stress. [ABSTRACT FROM AUTHOR]

Bias temperature instability (BTI) and hot-carrier degradation (HCD) are among the most important reliability issues but are typically studied independently in an idealized setting. However, even though it is well understood that mixed BTI/HC degradation corresponds to a realistic scenario, there is only a limited number of studies available on the impact of mixed stress conditions. In this first part of the work, we present a thorough experimental study of the impact of mixed stress conditions on SiON pMOSFET characteristics, which contain a study at the single defect level. We focus on the contribution of single defects to the recoverable component of degradation. From an electrostatic point of view, recovery after mixed negative BTI (NBTI)/HC stress is typically attributed to charge carrier emissions by oxide defects near the source, which have been charged during stress. However, the experimental characterization of recovery after different stress conditions provides strong evidence that even defects located in the vicinity of the source can remain uncharged after mixed NBTI/HC stress, and thus do not contribute to the recovery signal. Consequently, the recoverable component can be negligibly small after certain stress conditions, which leads to the conclusion that a simple electrostatic model does not properly describe the behavior of recovery after mixed NBTI/HC stress. [ABSTRACT FROM AUTHOR]

We report considerable improvement in the hysteresis and reliability of MoS2 field-effect transistors (FETs) achieved by chemical vapor deposition (CVD) of single-layer MoS2 and dielectric encapsulation. Our results show that a high-quality 15-nm thick Al2O3 layer allows for an efficient protection of the devices from adsorbent-type trapping sites. Combined use of the CVD-grown MoS2 as a channel and encapsulation simultaneously leads to at least an order of magnitude smaller hysteresis and up to two orders of magnitude lower long-term drifts of the transistor characteristics. Together with high on/off current ratios ( \sim 10^\textsf 9 ) achieved in our devices, this presents a considerable advance in the technology of MoS2 FETs. As such, we conclude that both CVD growth of MoS2 and encapsulation present important technological steps toward reaching commercial quality standards of next-generation two-dimensional (2D) material technologies. [ABSTRACT FROM AUTHOR]

Charge trapping is one of the main reliability issues for GaN-based MIS-high-electron-mobility-transistor technologies. In this paper, we focus on the defects located at or close to the interface with the dielectric, which are responsible for the threshold voltage instability at positive gate bias conditions. We present a methodology to analyze the experimental data based on the nonradiative multiphonon model for charge trapping. In particular, we show how to extract the density of interface traps as a function of their activation energy from stress and recovery experiments performed at various temperatures. Our approach is applied to two GaN/AlGaN/SiN samples with different trapping properties, at temperatures ranging from −190 °C to 200 °C. We evaluate their response to forward bias stress and finally, we extract the activation energy distribution for electron capture and emission over a continuous energy range. [ABSTRACT FROM AUTHOR]

After nearly half a century of research into the bias temperature instability, two classes of models have emerged as the strongest contenders. One class of models, the reaction-diffusion models, is built around the idea that hydrogen is released from the interface and that it is the diffusion of some form of hydrogen that controls both degradation and recovery. Although various variants of the reaction-diffusion idea have been published over the years, the most commonly used recent models are based on nondispersive reaction rates and nondispersive diffusion. The other class of models is based on the idea that degradation is controlled by first-order reactions with widely distributed (dispersive) reaction rates. We demonstrate that these two classes give fundamentally different predictions for the stochastic degradation and recovery of nanoscale devices, therefore providing the ultimate modeling benchmark. Using detailed experimental time-dependent defect spectroscopy data obtained on such nanoscale devices, we investigate the compatibility of these models with experiment. Our results show that the diffusion of hydrogen (or any other species) is unlikely to be the limiting aspect that determines degradation. On the other hand, the data are fully consistent with reaction-limited models. We finally argue that only the correct understanding of the physical mechanisms leading to the significant device-to-device variation observed in the degradation in nanoscale devices will enable accurate reliability projections and device optimization. [ABSTRACT FROM AUTHOR]

In this context, the so-called bias temperature instability (BTI), which emerges as a drift of the threshold voltage of a transistor, is an essential criterion for determining the reliability of devices. 10.3390/cryst11091150 2 Yu D., Dong Y., Ruan Y., Li G., Li G., Ma H., Deng S., Liu Z. Photo-Excited Switchable Terahertz Metamaterial Polarization Converter/Absorber. The impact of these defects on the device performance itself manifests as a drift in the performance of the MOS transistors over time. [Extracted from the article]

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit's performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too. [ABSTRACT FROM AUTHOR]

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage. [ABSTRACT FROM AUTHOR]

Ge-based Schottky diodes find applications in high-speed devices. However, Fermi-level pinning is a major issue for the development of Ge-based diodes. This study fabricates a Pt/carbon paste (CP)/Ge Schottky diode using low-cost CP as an interlayer. The Schottky barrier height (ΦB) is 0.65 eV for Pt/CP/n-Ge, which is a higher value than the value of 0.57 eV for conventional Pt/n-Ge. This demonstrates that the CP interlayer has a significant effect. The relevant junction mechanisms are illustrated using feasible energy level band diagrams. This strategy results in greater stability and enables a device to operate for more than 500 h under ambient conditions. This method realizes a highly stable Schottky contact for n-type Ge, which is an essential element of Ge-based high-speed electronics. [ABSTRACT FROM AUTHOR]

To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage over time. With ongoing miniaturization of the transistors towards a few tens of nanometer small devices the drift of the threshold voltage is observed to proceed in discrete steps. Quite interestingly, each of these steps correspond to charge capture or charge emission event of a certain defect in the atomic structure of the device. This observation paves the way for studying device reliability issues like BTI at the single-defect level. By considering single-defects the physical mechanism of charge trapping can be investigated very detailed. An in-depth understanding of the intricate charge trapping kinetics of the defects is essential for modeling of the device behavior and also for accurate estimation of the device lifetime amongst others. In this article the recent advancements in characterization, analysis and modeling of single-defects are reviewed. [ABSTRACT FROM AUTHOR]

Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO 2 technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies. [ABSTRACT FROM AUTHOR]

In this paper, we propose an asymmetric radiation-hardened 10T (AS10T) SRAM cell and analyze the impact of bias temperature instabilities (BTI) on the single event upset of the modified structure. For this, we make use of a read decoupled circuit to improve the stability of the reading cycle, and a charge booster circuit to increase the critical charge at the sensitive node of the SRAM cell. First, we compare the noise margin of several reference cells and can clearly observe that the read static noise margin (RSNM) of AS10T is 3.25× higher than as can be achieved for the 6T SRAM cell. This improvement is due to the read decoupled path used for the read operation. To analyze the soft-error hardening, we calculate the critical charge and observe that the critical charge of the proposed AS10T cell exceed the same parameter of other SRAM cells. Further, we perform critical charge simulations and stability analysis considering BTI and observe that the AS10T SRAM cell is also less affected by BTI as the reference cells. [ABSTRACT FROM AUTHOR]