9 results on '"Xue, Zhongming"'
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2. Analysis of Low-Frequency 1/f Noise Characteristics for MoTe 2 Ambipolar Field-Effect Transistors.
- Author
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Zhang, Bing, Hu, Congzhen, Xin, Youze, Li, Yaoxin, Xie, Yiyun, Xing, Qian, Guo, Zhuoqi, Xue, Zhongming, Li, Dan, Zhang, Guohe, Geng, Li, Ke, Zungui, and Wang, Chi
- Subjects
FIELD-effect transistors ,PINK noise ,ELECTRONIC noise ,TRANSITION metals - Abstract
Low-frequency electronic noise is an important parameter used for the electronic and sensing applications of transistors. Here, we performed a systematic study on the low-frequency noise mechanism for both p-channel and n-channel MoTe
2 field-effect transistors (FET) at different temperatures, finding that low-frequency noise for both p-type and n-type conduction in MoTe2 devices come from the variable range hopping (VRH) transport process where carrier number fluctuations (CNF) occur. This process results in the broad distribution of the waiting time of the carriers between successive hops, causing the noise to increase as the temperature decreases. Moreover, we found the noise magnitude for p-type MoTe2 FET hardly changed after exposure to the ambient conditions, whereas for n-FET, the magnitude increased by nearly one order. These noise characteristics may provide useful guidelines for developing high-performance electronics based on the emerging transition metal dichalcogenides. [ABSTRACT FROM AUTHOR]- Published
- 2022
- Full Text
- View/download PDF
3. Highly Efficient Fully Integrated Multivoltage-Domain Power Management With Enhanced PSR and Low Cross-Regulation.
- Author
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Guo, Zhuoqi, Li, Dan, Zhang, Bing, Xue, Zhongming, Dong, Li, Chen, Zeqiang, Xiong, Yuhao, and Geng, Li
- Subjects
DC-to-DC converters ,POWER resources ,SYSTEMS on a chip ,ELECTROMAGNETIC interference ,CAPACITOR switching - Abstract
Multivoltage domains are urgently needed in modern system on chips (SoCs), while existing solutions such as switched dc−dc converter, switched capacitor converter, and low-dropout regulator (LDO) do not generate multivoltage domains conveniently and inexpensively. This article presents a highly efficient fully integrated power management strategy to provide the multiple voltage domains. The proposed architecture stacks a main LDO and several auxiliary push−pull regulators (APPRs) to generate multiple voltages for various loads in one SoC chip. The APPR regulates the load current by either absorbing or providing the additional current, which stabilizes the output voltages, increases the power supply rejection (PSR) and decreases the cross-regulation. A prototype with two output terminals is implemented with a standard 0.18-μm CMOS technology. The whole system achieves high power efficiency of 96.5% and high PSR of −62 and −142 dB for upper and lower outputs, respectively. The chip area is 980 μm × 500 μm and the total quiescent current is 239 μA. In addition, all off-chip components are eliminated, which is favorable for monolithic realization. The reduced system cost and the reduced electromagnetic interference also simplify the power management significantly, which helps to enable low-power and compact SoCs. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
4. An Open Loop Digitally Controlled Hybrid Supply Modulator Achieving High Efficiency for Envelope Tracking With Baseband up to 200-MHz.
- Author
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Chen, Zeqiang, Xia, Qin, Dong, Li, Fan, Shiquan, Han, Kefeng, Guo, Zhuoqi, Xue, Zhongming, and Geng, Li
- Subjects
ELECTRONIC modulators ,BASEBAND ,TELECOMMUNICATION systems ,POWER amplifiers ,ALGORITHMS ,FOURIER transforms - Abstract
Envelope tracking (ET) is an effective way to improve the efficiency of power amplifier (PA) for 5G communication systems. To understand the restriction of the hybrid supply modulator (HSM) for ultra-wide band ET applications, an extended power loss model and a Short Time Fourier Transform (STFT) methodology are put forward to be the fundamental guide of the control methodology. An average voltage alignment (AVA) algorithm is proposed, which aligns the current waveforms by using pre-cached envelope signals to reduce the power loss due to the mismatch. Furthermore, a digital low pass filter (LPF) is integrated in the AVA controller, aiming at eliminating the necessity of very high-speed switches in HSM, which reduces the difficulty of hardware facility. The prototype chip is fabricated with a standard $0.18~\mu \text{m}$ CMOS technology and fulfilled with the discrete components on the PCB to verify the methodology and the system. Measurement results show that the proposed method extends the tracking bandwidth up to 200-MHz, and achieves 20% efficiency increment with the maximum 20 MHz switching frequency decrement comparing to the normal hysteresis comparison logic. A GaAs PA is introduced to measure the system linearity, and the ACPR of ET PA reaches −32 dBc. The proposed strategy successfully push the HSM ET application to hundreds of MHz compared with the previous level of 10-MHz. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
5. Topological Classification-Based Splitting–Combining Methodology for Analysis of Complex Multi-Loop Systems and Its Application in LDOs.
- Author
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Guo, Zhuoqi, Li, Haiqi, Li, Dan, Fan, Shiquan, Gui, Xiaoyan, Xue, Zhongming, Chen, Zeqiang, and Geng, Li
- Subjects
MATHEMATICAL complex analysis ,TRANSFER functions - Abstract
Multiple loops have been used extensively to enhance the system performance in various applications. However, the increasing complexity of multi-loop systems also makes them much more difficult to analyze and implement. In this paper, a new methodology to analyze multi-loop system is proposed. In the proposed framework, multi-loop systems are regarded to be built upon of sub-modules of cascade, parallel adding, and feedback units, and then, they are simplified following a certain procedure based on the correlation of the Bode characteristics of the segmented sub-modules. Applying this methodology, the Bode plot and the transfer function of the system can be easily obtained with the system properties of gains, zeros, and poles. Two examples are provided as demonstrators, including a multi-loop low-dropout regulator (LDO) from literature, and a newly designed multi-loop LDO aiming at enhancing the stability over a wide load range, which show that the Bode plot and the transfer function can be obtained more intuitively and rapidly. Excellent agreements among theory, simulations, and measurements are confirmed, which verify the proposed method. It can help designers to gain more intuitions and insights on multi-loop systems from both circuit and device perspectives, which is also an effective tool for both stability analysis and circuit design. [ABSTRACT FROM AUTHOR]
- Published
- 2019
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- View/download PDF
6. A 13.56 MHz, 94.1% Peak Efficiency CMOS Active Rectifier With Adaptive Delay Time Control for Wireless Power Transmission Systems.
- Author
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Xue, Zhongming, Fan, Shiquan, Li, Dan, Zhang, Lina, Gou, Wei, and Geng, Li
- Subjects
WIRELESS power transmission ,TIME delay systems ,DELAY lines ,HIGH voltages - Abstract
In this paper, an adaptive delay time control (ADTC)-based CMOS active rectifier is proposed. Compared with previous active rectifiers, power-hungry comparators are eliminated in this structure. Instead, optimal on/off time of the power switches is generated by two current controlled delay lines (CCDLs), which enables drastic power reduction of the active rectifier. In addition, the multiple-pulsing problem is eliminated due to the introduced control mechanism. The high-precision on/off control at picosecond-level precision removes the reverse current of the rectifier and guarantees high voltage conversion rate (VCR) and power conversion efficiency (PCE). The active rectifier is fabricated with a standard 0.18- $\mu \text{m}$ CMOS process. The experimental results show that the quiescent power consumption of the rectifier is less than 230 $\mu \text{W}$. The current conduction angle reaches the optimal state under different input and load conditions because of the adaptive adjustment. The peak PCE is 94.1% at the output power of 10.63 mW. The PCE is enhanced by 6.7% compared with the previous design. The maximum output power of 34.1 mW is achieved with input ac amplitude of 2.5 V. The proposed low-power high-efficiency active rectifier gives a favorable solution for the wireless power transmission systems. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
7. VRSPV Soft-Start Strategy and AICS Technique for Boost Converters to Improve the Start-Up Performance.
- Author
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Fan, Shiquan, Xue, Zhongming, Guo, Zhuoqi, Wang, Yan, and Geng, Li
- Subjects
ENERGY conversion ,CAPACITORS ,ELECTRIC potential ,PRINTED circuits ,ELECTRIC measurements - Abstract
Soft-start strategy is very important for boost converters to guarantee the stability of the output voltage. However, previous methods may cause large initial inrush current and long output voltage settling time. In this paper, a variable ramp-slope with predefined voltage (VRSPV) soft-start strategy is proposed. As a result, one branch of the initial inrush current is successfully eliminated and the output settling time of the boost converter is shortened by using the variable slope soft-start voltage. Also, an adaptive inrush current suppressing (AICS) technique is designed. The series resistance of the output capacitor is adaptively regulated by AICS technique to further suppress the initial inrush current. Finally, the VRSPV strategy and AICS technique are combined and implemented in a voltage-mode boost converter. The measurement results show that the peak initial inrush current and settling time are decreased by 60% and 40%, respectively. The output voltage of the boost converter increases smoothly during the soft-start period and finally achieves stability. The proposed method of combining VRSPV strategy and AICS technique is very suitable to be integrated on a chip to save the printed circuit board area and cost. [ABSTRACT FROM AUTHOR]
- Published
- 2016
- Full Text
- View/download PDF
8. A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications.
- Author
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Song, Yan, Xue, Zhongming, Xie, Yi, Fan, Shiquan, and Geng, Li
- Subjects
ENERGY consumption ,SUCCESSIVE approximation analog-to-digital converters ,COMPLEMENTARY metal oxide semiconductors ,LOGIC circuits ,CMOS memory circuits - Abstract
This paper proposes a fully differential 10-bit energy efficient successive approximation register (SAR) analog-to-digital converter (ADC) by using incremental converting method. The voltage difference of the input between two successive samples is acquired and resolved. A judge window is properly designed, and several conversion steps of significant bits could be skipped when the voltage difference is within the preset window. Thus, the power consumptions of the digital-to-analog converter (DAC), logic circuit, and comparator are greatly saved. Moreover, the differential structure also helps to suppress common mode noise and even harmonic noise. The design is implemented with a standard 0.18- \mu\textm CMOS technology. Test results show that the power consumption of the ADC with the proposed algorithm is reduced by at least 42.8% comparing to the conventional structure. The measured DNL and INL are within 0.29 LSB and 0.80 LSB, respectively. At a 0.6-V supply and a 200-kS/s sampling rate, the ADC achieves an ENOB of 9.34 and a figure-of-merit of 8.87 fJ/conv.-step. [ABSTRACT FROM AUTHOR]
- Published
- 2016
- Full Text
- View/download PDF
9. Area-Efficient On-Chip DC–DC Converter With Multiple-Output for Bio-Medical Applications.
- Author
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Fan, Shiquan, Xue, Zhongming, Lu, Hao, Song, Yan, Li, Haiqi, and Geng, Li
- Subjects
CASCADE converters ,ENERGY consumption ,TRANSISTORS ,SWITCHING circuits ,ELECTRIC inductors - Abstract
Multiple-supply are required to minimize the power consumptions in bio-implant systems. A single-inductor multiple-output (SIMO) switching converter is one of the solutions. But it has inherent problems which block the applications in the embedded biomedical systems. In this paper, a circuit arrangement for providing multiple outputs based on low-dropout (LDO) regulator is proposed. The regulating transistor of LDO is time-shared by N output legs. Two error amplifiers (EAs) are utilized in the topology, irrespective of number of the output legs. The corresponding switching strategy alleviates the difficulties associated with controlling multiple switching functions for conventional time-sharing methods, and thus, permits multiple outputs to be generated easily. A prototype multiple-output LDO (MOLDO) regulator with four output legs was fabricated with a standard 0.35 \mu\ m CMOS process. The measurement results verify the good performance of this design such as no cross regulation (CR), small ripples, and less power consumption. Moreover, it does not require inductor and presents low total harmonic distortion, which is very suitable for bio-implant fields. [ABSTRACT FROM PUBLISHER]
- Published
- 2014
- Full Text
- View/download PDF
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