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The effect of incorporating different percentages of hydrophobic and hydrophilic nanosilica (HPB and HPL NS) particles and chain extender (CE) on the mechanical behavior of poly(lactic acid)/poly(butylene adipate‐co‐terephthalate) (PLA/PBAT) blends was evaluated. The mechanical behavior of the samples was explained using different theoretical models. Microscopic studies showed that adding both types of NS particles and CE led to more uneven surfaces for blends. Also, no obvious aggregations were observed in both blend nanocomposites, and both kinds of NS particles were mainly present in the PBAT phase. Except for the blend containing 1 phr HPB NS particles, which revealed a continuous morphology, all the PLA/PBAT blends containing both types of NS particles indicated a droplet‐matrix morphology. The more the NS content, the more uniform the PBAT distribution. Adding CE in the blends improved Young's modulus, yield strength, and elongation‐at‐break to a particular loading of CE (2 phr), while these properties were diminished after introducing more CE. Also, the most improvements in the yield strength (45%) and Young's modulus (35%) were seen for the PLA/PBAT (75/25 w/w) containing 2 phr CE and 5 phr HPL NS particles. Besides, a good agreement was observed for experimental values and theoretical models for all samples. [ABSTRACT FROM AUTHOR]

As a packaging materials candidate, based on a polylactic acid/ polybutylene adipate terephthalate (PLA/PBAT) blends (90/10 and 75/25 wt/wt) containing 1, 3, and 5 phr hydrophilic (HPL) and hydrophobic (HPB) nanosilica (NS) particles in the presence of a multifunctional epoxide compatibilizer were prepared by melt mixing, in a twin-screw extruder. Scanning electron microscopic studies confirmed a matrixdroplet morphology with finer dispersed domains at higher NS content. Energy dispersive spectroscopy mapping also indicated uniform dispersion of NS in blends, with some agglomerates at higher content of nanoparticles. Moreover, transmission electron microscope was applied to study the impact of nanofillers' localization on the systems' morphology. It was observed that NS particles localized at the PLA-PBAT interface. In addition, thermogravimetric analysis (TGA) was used to investigate thermal stability and thermal degradation kinetics. Data indicates that hydrophobic NS improved thermal stability. The activation energy of degradation was calculated using several techniques of data modeling, including Friedman, Flynn-Ozawa-Wall, and Kissinger-Akahira-Sunose models. Among blend nanocomposites, 75/25 blend containing 5 phr HPB NS had the maximum degradation activation energy, suggesting that this sample had the most resistance to heat degradation. The intensity of the TGA/FTIR peaks of the evolved products was found to be correlated with the activation energy. The Criado's technique was also used to investigate the changes in the thermal degradation mechanism. [ABSTRACT FROM AUTHOR]

Deep Quantization (below eight bits) can significantly reduce the DNN computation and storage by decreasing the bitwidth of network encodings. However, without arduous manual effort, this deep quantization can lead to significant accuracy loss, leaving it in a position of questionable utility. We propose a systematic approach to tackle this problem, by automating the process of discovering the bitwidths through an end-to-end deep reinforcement learning framework (ReLeQ). This framework utilizes the sample efficiency of proximal policy optimization to explore the exponentially large space of possible assignment of the bitwidths to the layers. We show how ReLeQ can balance speed and quality, and provide a heterogeneous bitwidth assignment for quantization of a large variety of deep networks with minimal accuracy loss ($\leq$ ≤ 0.3% loss) while minimizing the computation and storage costs. With these DNNs, ReLeQ enables conventional hardware and custom DNN accelerator to achieve $~2.2\times$ 2. 2 × speedup over 8-bit execution. [ABSTRACT FROM AUTHOR]

The need to support various machine learning (ML) algorithms on energy-constrained computing devices has steadily grown. In this article, we propose an approximate multiplier, which is a key hardware component in various ML accelerators. Dubbed SiMul, our approximate multiplier features user-controlled precision that exploits the common characteristics of ML algorithms. SiMul supports a tradeoff between compute precision and energy consumption at runtime, reducing the energy consumption of the accelerator while satisfying a desired inference accuracy requirement. Compared with a precise multiplier, SiMul improves the energy efficiency of multiplication by 11.6x to 3.2x while achieving 81.7-percent to 98.5-percent precision for individual multiplication operations (96.0-, 97.8-, and 97.7-percent inference accuracy for three distinct applications, respectively, compared to the baseline inference accuracy of 98.3, 99.0, and 97.7 percent using precise multipliers). A neural accelerator implemented with our multiplier can provide 1.7x (up to 2.1x) higher energy efficiency over one implemented with the precise multiplier with a negligible impact on the accuracy of the output for various applications. [ABSTRACT FROM AUTHOR]

Editor's notes: [ABSTRACT FROM AUTHOR]

This article develops a comprehensive technique for failure prediction in the field for many-core processors to address wear out in harsh environments for logic and static RAM (SRAM). The authors develop three principles. First, virtually aging a processor by momentarily reducing its voltage exposes wear-out failure. Second, sampled redundancy can be used to capture logic wear-out failures because their underlying fault model is delay faults, which makes them poorly suited for using test-vector-based techniques. Third, wear out on SRAMs decreases their noise margin, and the end results can be effectively modeled as a stuck-at fault, thus allowing asymmetric checkers like built-in self-test to work effectively. The authors' design comprises two components (Aged-SDMR, which combines sampling and dual-modular redundancy, and Aged-AsymChk, which uses an asymmetric checker); has a simple implementation; and delivers low complexity, low overheads, and high accuracy. In addition to ensuring no corruptions or missed errors from wear-out failures, the full system predicts failures within 0.4 days for logic and within milliseconds for SRAM after their appearance. Furthermore, compared to SRAMs protected only with error-correcting code and decommissioned on first failure, the authors extend lifetime by 14 months on average. [ABSTRACT FROM AUTHOR]

Relaxing the traditional abstraction of "near-perfect" accuracy in hardware design can yield significant gains in efficiency, area, and performance. To exploit this opportunity, there is a need for design abstractions and synthesis tools that can systematically incorporate approximation in hardware design. The authors define Axilog, a set of language extensions for Verilog that provides the necessary syntax and semantics for approximate hardware design and reuse. Axilog lets designers safely relax the accuracy requirements in the design while keeping the critical parts strictly precise. Axilog is coupled with a Safety Inference Analysis that automatically infers the safe-to-approximate gates and connections from the annotations. The analysis provides formal guarantees that the safe-to-approximate parts of the design strictly adhere to the designer's intentions. The authors devise two synthesis flows that leverage Axilog's framework for safe approximation; one by relaxing the timing requirements and the other through gate resizing. They evaluate Axilog using a diverse set of benchmarks that gain 1.54× average energy savings and 1.82× average area reduction with 10 percent output quality loss. The results show that the intuitive nature of the language extensions coupled with the automated analysis enables safe approximation of designs even with thousands of lines of code. [ABSTRACT FROM PUBLISHER]

Custom instructions potentially improve execution speed and code compression of embedded applications. However, more efficient custom instructions need higher number of simultaneous registerfile accesses. Larger registerfiles are more power hungry with complex forwarding interconnects. Therefore, due to the limited ports of the base processor registerfile, size and efficiency of custom instructions could be generally limited. Recent researches have focused on overcoming this limitation by some innovative architectural techniques supplemented with customized compilations. However, to the best of our knowledge there are few researches that take into account the complete pipeline design and implementation considerations. This paper proposes a customized instruction set and pipeline architecture for an optimized embedded engine. The proposed architecture increases the performance by enhancing the available registerfile data bandwidth through register access pipelining. The achieved improvements are made by introducing double-word custom instructions whose registerfile accesses are overlapped in the pipeline. Potential hazards in such instructions are resolved by the introduced pipeline backwarding concept, yielding higher performance and code compression. While we study the effectiveness of the proposed architecture on domain-specific workloads from packet-processing benchmarks, the developed framework and architecture are applicable to other embedded application domains. [ABSTRACT FROM AUTHOR]

This paper presents a new merit function for custom instruction selection phase of the design flow of application-specific instruction-set processors (ASIPs) in the presence of an area budget constraint. In contrast to nearly all of the previously proposed approaches where ratio of the ASIP speed to layout area is used as a merit function to select the candidate custom instructions (CIs), we show that a merit function based on normalized cycle saving and area function can result in better CI selections in terms of the achievable speedup under a given area budget for both greedy and branch-and-bound techniques. The efficacy of the proposed approach is assessed by comparing the results of using the proposed and conventional merit functions for different benchmarks. The comparison points toward an average (maximum) speed enhancement of 3.65 % (27.4 %) for the proposed merit function compared to the conventional merit functions. [ABSTRACT FROM AUTHOR]