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Nonvolatile memory (NVM)‐based neuromorphic computing has been attracting considerable attention from academia and the industry. Although it is not completely successful yet, remarkable achievements have been reported pertaining to synaptic devices that can leverage NVM capable of storing multiple states. The analog synaptic devices performing computation similar to biological nerve systems are crucial in energy‐efficient analog neuromorphic computing systems. To use NVM as an analog synaptic device, researchers focus on improving device characteristics. Among various characteristics, the most challenging one is linearity and symmetry of synaptic weight update that is required for on‐chip training. In this regard, this review paper discusses recent synaptic device improvements focusing on novel schemes tailored for each NVM device to improve the linearity and symmetry. In addition to device‐level studies, recent research achievements are reviewed expanded up to chip‐level studies because in realizing neuromorphic hardware systems beyond a single synaptic device, several considerations and requirements are needed to confirm for high‐level design, and accordingly, cooptimize among synaptic devices, synapse arrays, electrical circuits, neural networks, algorithms, and implementation. Also, this review introduces various circuit and algorithmic approaches to compensate for the non‐ideality of the analog synaptic device. [ABSTRACT FROM AUTHOR]

Implementations of artificial neural networks that borrow analogue techniques could potentially offer low-power alternatives to fully digital approaches1–3. One notable example is in-memory computing based on crossbar arrays of non-volatile memories4–7 that execute, in an analogue manner, multiply–accumulate operations prevalent in artificial neural networks. Various non-volatile memories—including resistive memory8–13, phase-change memory14,15 and flash memory16–19—have been used for such approaches. However, it remains challenging to develop a crossbar array of spin-transfer-torque magnetoresistive random-access memory (MRAM)20–22, despite the technology’s practical advantages such as endurance and large-scale commercialization5. The difficulty stems from the low resistance of MRAM, which would result in large power consumption in a conventional crossbar array that uses current summation for analogue multiply–accumulate operations. Here we report a 64 × 64 crossbar array based on MRAM cells that overcomes the low-resistance issue with an architecture that uses resistance summation for analogue multiply–accumulate operations. The array is integrated with readout electronics in 28-nanometre complementary metal–oxide–semiconductor technology. Using this array, a two-layer perceptron is implemented to classify 10,000 Modified National Institute of Standards and Technology digits with an accuracy of 93.23 per cent (software baseline: 95.24 per cent). In an emulation of a deeper, eight-layer Visual Geometry Group-8 neural network with measured errors, the classification accuracy improves to 98.86 per cent (software baseline: 99.28 per cent). We also use the array to implement a single layer in a ten-layer neural network to realize face detection with an accuracy of 93.4 per cent.A crossbar array of magnetic memory to execute analogue in-memory computing has been developed, and performs image classification and facial detection at low power. [ABSTRACT FROM AUTHOR]