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A beam monitor system is being developed for the cool storage ring (CSR) external-target experiment (CEE) at the Heavy Ion Research Facility in Lanzhou (HIRFL). The beam monitor is required to measure the lateral position of each beam particle with spatial resolution less than 50 m and with beam rates up to 1 MHz. As the beam intensity increases, the build-up of slow-moving positive ions created from the ionization of the detector gas by the beam leads to a significant distortion of the nominal electric field in the drift region. In this work, simulation studies of the beam monitor are performed, in particular the space charge effect and the correction strategy. It shows that the space charge at the nominal drift electric field of 700 V/cm modifies the electric field in the sensitive volume by roughly 5 in both the drift and transverse directions. The distortion on the measured position is up to 0.35 mm in the 5 region of the beam profile. The expected spatial resolution of 500 MeV/u U ion is 34.5 m considering the pixel noise of 400 and the 100 m 1 mm pixel size of the charge sensor chip in the selected gas mixture. [ABSTRACT FROM AUTHOR]

The cool storage ring (CSR) external-target experiment (CEE) will be the first large-scale nuclear physics experiment at the Heavy Ion Research Facility in Lanzhou (HIRFL). The beam monitor, designed to measure the lateral position of each beam particle, will improve the precision of primary vertex reconstruction otherwise determined by the time projection chamber (TPC) and multi-wire drift chambers (MWDCs). The beam monitor mainly contains two gaseous ionization sub-detectors, each measuring one lateral coordinate of the beam. The design requirements include the spatial resolution of m, the two-particle separation capability of s, the rate capability of pps, and small material budget. It features novel front-end pixel chips for both charge sensing and readout functions. The first prototype, utilizing the common-purpose Topmetal-II-chips, has been developed and tested; the second one, deploying the custom-designed Topmetal-CEEv1 chips, is currently being assembled. In this paper we will present the detector specifications, design and test of the prototypes, in particular the charge sensing and readout chips. [ABSTRACT FROM AUTHOR]

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 m. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back. [ABSTRACT FROM AUTHOR]