Search

This paper aims to review the main research points regarding DC fast charging stations. At the beginning, the paper addresses an overview of DC fast charging standards, galvanic isolation, EV powertrain, and some examples of real DC fast chargers. This part highlights that DC fast chargers are usually connected to an AC network or microgrid, whereas DC microgrids would be a better choice to increase the charging efficiency and reduce the costs. However, the lack of standards in terms of protection and metering made their spread limited for the moment. Moreover, the paper describes the power converter topologies typically adopted in DC fast charging stations and emerging solutions to interface EVs with both 400 V and 800 V powertrains. Then, the paper explains the main architectural features of DC fast charging stations connected to DC networks or microgrids because of their potential to become the standard infrastructure in this field. Furthermore, the energy management strategies for DC fast charging stations are discussed, taking into account their relevant goals. Finally, cybersecurity issues of charging stations are covered, also considering their impact on grid and electric vehicle supply equipment, and providing a particular discussion regarding DC fast charging stations.

This paper presents an approach and a corresponding laboratory infrastructure for multi-hardware-in-the-loop (M-HiL) testing of power converters and intelligent electronic devices (IEDs) with wide area features for power system monitoring and control. The basis for the testing environment is a digital real-time simulation (RTS) platform which can be utilized for phasor-based or hybrid phasor and electromagnetic transient (EMT) power system simulation. A high-bandwidth power amplifier is used for interfacing the real-time simulated power system to the power hardware. The necessary elements and their interfaces required for realizing the M-HiL testing are highlighted in the paper. Finally, a complete example of an M-HiL test based on real-time simulation of the Nordic 44 (N44)-bus power system model is presented. The test setup includes two phasor measurement units (PMUs) with their corresponding communication layers and a converter configuration for scaled emulation of the HVDC transmission system of an offshore wind farm. The configuration also includes a grid forming converter unit operated in parallel to the grid-side HVDC terminal. The presented test demonstrates how a grid forming converter operated as a Virtual Synchronous Machine (VSM) can provide frequency support to the Nordic power system and how this support would be recorded by the PMUs.

One of the main advantages of multi-level inverters (MLI) is their ability to achieve high power quality and high efficiency power conversion. With the emergence of wide-band-gap (WBG) devices, the tendency has grown towards using high switching frequencies to improve converters’ output power quality and minimize switching harmonic filters footprint. While high-frequency switching finds significant success in low and medium-power applications, it is not the best practice to reduce the filter size when applied to medium voltage (MV) high power (HP) inverters implemented with high voltage levels. In this paper, we show that the least filtering requirements for MV HP higher level inverters is achieved using the modulation strategy with the least switching, i.e., the staircase modulation. The paper compares the harmonic filter requirements and power losses for low-frequency and high-frequency pulse-width-modulated MLI. The analysis shows that low-frequency switching not only achieves the lowest losses, but also produces the lowest line-to-line voltage total harmonic distortion (THD), which allows eliminating both voltage and current harmonic filters in higher level inverters. Simulation results are provided to verify the theoretical analysis on the THD, and experiments on a 1 kW, 600Vdc MLI are presented to compare efficiency for low- and high-frequency modulation.

This paper introduces a novel control approach for an LCC-S Wireless Power Transfer (WPT) system. The system's output voltage regulation is achieved through a variable inductor, leveraging magnetic core saturation. A comprehensive design methodology for the variable inductor tailored to the desired control characteristics is presented. Addressing a significant gap in the current literature, the paper addresses the non-trivial challenge of developing a small signal model that correlates output voltage variations with changes in inductance. To fill this gap, the proposed approach pioneers a transfer function, providing an accurate description of this dynamic. Additionally, a closed-loop control system is proposed for prompt adjustment of the output voltage. The efficacy of this control system is demonstrated even in the face of rapid load variations or misalignment, ensuring reliable regulation. The robustness and effectiveness of the proposed approach are substantiated through extensive experimental measurements, validating the theoretical and simulation results.

In this paper, a new synchronous rectified converter with ultra-low output current ripple and high voltage attenuation is proposed. The presented converter can achieve soft switching without requiring any additional active components, leading to high efficiency while maintaining the simplicity of conventional converters. Other main features of the proposed circuit are inherent shoot-through protection, reduced current stress of the semiconductors due to the coupled inductor, and low voltage stress across the low-side MOSFET. In addition, a pulse frequency modulation control scheme is used, which allows for an extended soft-switching range without imposing an excessive circulating current at light loads. The steady-state analysis and experimental results from a 120 W prototype are presented in this paper.

Ground power unit (GPU) converters are often required to efficiently manage power distribution in various ground-based applications, necessitating designs that balance performance, and cost-effectiveness. In this paper, a novel nine-level output converter using a single voltage source, 8 unidirectional and one bidirectional MOSFET switches, and two capacitors has been presented to utilize in GPUs. A simple modulation algorithm (PWM) has been applied to achieve a THD of 3.1% on the output voltage at 115/200 V and 400 Hz without the need for additional filtering. With a relatively small output filter, the THD is further reduced to less than 1%. The proposed converter utilized a lower number of devices to output a nine-level staircase in comparison to existing converters. Additionally, the proposed converter employs inherent self-voltage balancing for capacitor voltages, thereby simplifying the control algorithm. In this paper, the topology analysis, modulation algorithm, capacitor calculation, loss, efficiency, and performance analysis of the proposed topology have been presented. The proposed circuit has been compared to recently published papers in terms of switch, capacitor, diode, and source numbers. The theoretical and experimental performance of the topology has been verified by simulation on PSIM software and experimental setup.

This paper proposes a generalized space vector modulation (SVM) strategy for 3-level neutral-point-clamped (NPC) converters. The proposed strategy, here referred to as multiphase 3-level SVM (MP3L-SVM), is developed as a generic modulation technique applicable for 3-level NPC converters with any number of phases, while for showcasing in this paper the proposed MP3L-SVM is applied to a wind turbine with a direct drive multiphase permanent magnet generator (PMG) whose output is rectified using a 3-level NPC converter before connection to a high-voltage DC (HVDC) grid. A key challenge in 3-level NPC converters is maintaining a balanced voltage across the HVDC-link capacitors, particularly at low speeds. To address this issue, the paper integrates the proposed MP3L-SVM strategy with a voltage balancing algorithm (VBA), which mitigates capacitor voltage imbalances by choosing the three nearest switching states that result in minimal energy deviations across the capacitors. The paper discusses the mathematical modeling of a multiphase PMG interfaced to a 3-level NPC and derives generalized models that govern the proposed strategy based on a visual space vector diagram (SVD). Analytical models are validated through simulations across various 3-level NPC configurations, including 3-phase, 6-phase, and 9-phase NPC converters. Further, the analytical models and simulation results are validated by test results from a scaled-down laboratory prototype 3-level NPC converter that has been prototyped in-house.

Converters that produce an isolated dc output from a three-phase mains supply are often required. Moreover, input power factor correction (PFC) functionality is essential. A standard two-stage conception with ac/dc and dc/dc converters may be used. However, a single-stage or quasi-single-stage solution can simplify the circuitry and increase efficiency; therefore, many variants of single-stage converters have been researched and published. This paper introduces a novel quasi-single-stage resonant topology with an integrated transformer. Additionally, an original control structure is proposed. This converter enables full control over the output dc voltage and current. Another benefit of the proposed converter is a relatively low complexity of its power circuit and control compared to other single-stage converters. The operation principle of the power circuit is explained and the control strategy is also analyzed in detail. A description of the integrated transformer together with aspects of the resonant circuit design are presented. A simulation of the entire converter was performed and evaluated. Furthermore, a test-bench prototype was designed and constructed and is outlined in this paper. The test-bench measurement results are provided and compared to the simulation results. Power factor and efficiency measurements in terms of their dependence on the output voltage and current are included.

The fault clearance time in the power system can vary from a few milliseconds to a few hundred milliseconds. Power electronics converters should be able to provide the increased current during faults without failing due to thermal limits. Hence, the heat generated in the semiconductor chip due to the over-current (OC) should be removed as soon as it is generated. In this paper, cooling by heat-absorbing material has been investigated on the top, bottom, and top $+$ bottom of the SiC MOSFET chip using COMSOL simulations for OCs. The heat-absorbing materials considered in the paper are copper, graphite, and aluminum. The maximum allowed chip temperature is assumed to be 250 °C since SiC devices do not fail in this range of temperature. It is concluded that the cooling on the top of the chip has the best performance among the three arrangements discussed in the paper in terms of OC duration and steady-state temperature. Another conclusion is that copper has the best performance due to higher thermal capacity for the same volume of the heat-absorbing material.

Hybrid switched-capacitor converters (HSCCs) have gained attention due to their promising efficiency and power density compared to traditional inductor- or capacitor-based converters. However, with the recent development of various HSCC topologies, it has become increasingly challenging to choose the most suitable one for a particular application. To address this challenge, this paper proposes a benchmarking framework that enables direct comparison of direct HSCC topologies based on various performance metrics such as passives volume and bandwidth. The proposed approach, which compares all topologies at the same efficiency and output voltage ripple, provides guidelines for topology selection and optimization, ultimately contributing to wider industrial adoption and exploration of new topologies. Downloadable open-access code is also provided to recreate presented results and expand to other topologies not discussed in the paper.

This paper proposes a current-fed dual active bridge (DAB) converter with an asymmetric three-phase transformer, aiming to achieve high efficiency over a wide operating range. In the proposed converter, the neutral point (junction) of the three-phase transformer is clamped by the DC power supply on the primary side and by a capacitor on the secondary side, decoupling each phase of the transformer. This configuration enables transformers with different turn ratios, allowing for the selection of energizing phases according to the circuit condition. In order to show the effectiveness of the proposed converter, this paper models the power losses of the proposed converter and shows its efficiency characteristics through theoretical analysis. Furthermore, the efficient operating modes corresponding to the circuit and load conditions are indicated based on the theoretical analysis. Experiments using a 1 kW prototype demonstrate the validity of the theoretical analysis. Consequently, the efficiency characteristics obtained experimentally indicate similar trends from the theoretical analysis, confirming that the proposed converter operates efficiently over a wide range. Additionally, the proposed converter is compared using the analytical models to a DAB converter with a symmetric three-phase transformer. As a result, it is shown that the proposed converter can achieve an efficiency improvement of more than five percentage points (% points) under light loads, and the efficiency drop in specific operating points can be capped by 1.25% points.

Offshore wind is expected to be a major player in the global efforts toward decarbonization, leading to exceptional changes in modern power systems. Understanding the impacts and capabilities of the relatively new and uniquely positioned assets in grids with high integration levels of inverter-based resources, however, is lacking, raising concerns about grid reliability, stability, power quality, and resilience, with the absence of updated grid codes to guide the massive deployment of offshore wind. To help fill the gap, this paper presents an overview of the state-of-the-art technologies of offshore wind power grid integration. First, the paper investigates the most current grid requirements for wind power plant integration, based on a harmonized European Network of Transmission System Operators (ENTSO-E) framework and notable international standards, and it illuminates future directions. The paper discusses the wind turbine and wind power plant control strategies, and new control approaches, such as grid-forming control, are presented in detail. The paper reviews recent research on the ancillary services that offshore wind power plants can potentially provide, which, when harmonized, will not only comply with regulations but also improve the value of the asset. The paper explores topics of wind power plant harmonics, reviewing the latest standards in detail and outlining mitigation methods. The paper also presents stability analysis methods for wind power plants, with discussions centered on validity and computational efficiency. Finally, the paper discusses wind power plant transmission solutions, with a focus on high-voltage direct-current topologies and controls.

This survey provides a comprehensive review of hybrid circuit breakers and their applications in 1 kV to 800 kV, both alternating current and direct current systems. The paper introduces the research motivation and key applications of hybrid circuit breakers, followed by a detailed analysis on the generic structure and operation principles of four core components: the mechanical switch, the semiconductor devices, the energy absorbers, and the commutation switch. Critical challenges on the optimization of each component are identified and potential solutions are suggested. Moreover, the paper innovatively summarizes the system-level considerations that are critical for the holistic development of hybrid circuit breakers, such as current sensing, control latency, hardware in the loop validation, and integration of multiple HCBs for multi-terminal DC system protections. This review seeks to provide design considerations and streamline the prototyping process of hybrid circuit breakers from the component, topology and system integration perspectives, which will benefit the advanced protection equipment in emerging systems such as renewable energy integration, electrified transportation, and multi-port power systems.

Power electronics converters (PECs) are responsible for efficiently converting electrical energy between power generators, storage systems and power consumers/loads. The PECs are subjected to complicated power loading factors throughout their operations and, thus, are proven to have issues regarding lifetime. Therefore, according to the original equipment manufacturers and suppliers, the reliability of the PECs is a key priority in order to be widely used and accepted in the industries. In this context, this review article aims to provide a comprehensive overview of reliability assessment strategies and testing protocols for ensuring the lifetime requirements of PECs. In addition, the paper conducts a thorough investigation of various strategies that are employed to enhance reliability during the design and useful life phase, including the analysis of different types of failure mechanisms, identification of factors contributing to failures, and assessment of techniques for estimating and regulating junction temperatures to prolong the lifetime of the system under real-life operating conditions. Furthermore, the article highlights the challenges encountered in monitoring and predicting component degradation and outlines the crucial steps for conducting a functional safety analysis. Particular emphasis is provided on summarizing the different accelerated aging tests for power electronics converters used in automotive applications, as these tests have yet to be fully covered in previous literature. This study provides an overview and guidelines for understanding the reliability of PECs and identifying potential areas for future research. Finally, the paper concludes most of the ongoing research and innovations in this area and provides insights into the future trends and challenges in enhancing the reliability of power electronics converters.

The Si/SiC Cascode device has been widely accepted in various applications, however, its reliability issue still remains a major concern and needs to be extensively investigated. In this paper, the degradation of a 750 V Si/SiC Cascode device under repetitive short-circuit (SC) tests is investigated at 400 V DC-link voltage. Static and dynamic characteristics are measured before and after the repetitive SC cycles. As the SC cycle increases, the degradation of the device becomes gradually significant. By linking changes in electrical properties to metallization degradation, the physical mechanism of device degradation has been uncovered in depth. Experimental results show that the continuous stress under repetitive SC cycle leads to an increase in the on-state resistance of Si/SiC Cascode device. Finite-element-model (FEM) simulations show that due to the pad current crowding in the source region, the source Al metallization temperature of the SiC JFET rapidly increases to the melting point and undergoes reconstruction, resulting in a significant increase in the source Al metallization resistance. In addition, it is found by scanning electron microscopy (SEM) that the gate metal aluminum of SiC JFET chip also undergoes reconstruction, which is the reason for the degradation of the dynamic characteristics. The research in this paper will provide useful evidences for device manufactures to design Si/SiC Cascode device with high reliability.

This paper presents the analysis and optimization procedure of a two-stage bidirectional AC/DC power supply. The exemplary power supply consists of a silicon carbide based active front end and a dual active bridge DC/DC converter. It is designed to supply 600 V DC applications from universal low voltage AC grids with a power up to 6 kW. The paper includes the topology and design considerations, as well as an in-depth loss distribution analysis based on a validated loss model. The loss model is then utilized for an operation space optimization. A special focus is drawn to the loss model and the optimization: It is based on analytical equations optimized for a low calculation effort. This enables quick modeling of a large operation space. Those results can both be used to validate design considerations as well as to optimize operating parameters. The presented dynamic operating parameter optimization enables a loss reduction at full load by 14% and at half load by even 48%. By means of the optimization the operating area can be expanded, losses decreased, and thermal stress reduced.

As the demand for medium-voltage power semiconductors continues to rise, the super-cascode switch has emerged as a promising solution. This paper presents the design, implementation, and experimental evaluation of a 6.5 kV, 400 A super-cascode power module. This treatment includes an in-depth analysis of the theory of operation for this topology, as well as a set of design guidelines to facilitate the realization of practical implementations. To validate the functionality and performance of the realized prototype module, double-pulse test experiments were conducted under a wide range of operating conditions, deploying metrics specially targeted for the super-cascode switch. These experimental results demonstrate that adherence to the design guidelines provided in this paper yields a super-cascode switch with exceptional performance. In fact, the super-cascode module evaluated in this paper achieves switching performance on par with that of medium voltage SiC MOSFET modules, and far beyond that of medium voltage Si IGBT modules. Overall, this investigation contributes to the understanding of the factors driving the operation and performance of the super-cascode switch, especially under high current conditions.

The fast slew rates of wide bandgap semiconductors can produce common-mode currents that flow through the baseplates of multi-chip power modules. These currents increase the electromagnetic signature of these devices and force designers to reduce edge rates or add additional filters in order to meet compliance standards. Parasitic baseplate capacitances that exist within power module packaging are known to be a primary path for the flow of these common-mode currents. Unfortunately, the measurement techniques currently available to characterize these capacitances are either challenging to perform or require the internal interconnects to be removed. This paper proposes a simple and non-destructive measurement technique to characterize the baseplate capacitances of multi-chip power modules on a per-terminal basis. The technique can be performed with an impedance analyzer and does not require any special fixturing or alterations to the module. The measurement technique described in this paper is applied to three fully populated commercial modules and is validated by comparisons to the standard destructive measurement technique and finite-element analysis simulation software.

Power Line Communication (PLC) and Simultaneous Wireless Information and Power Transfer (SWIPT) are popular examples of applications, where power and information are transmitted simultaneously. In most cases, different devices have been used to generate the power and communication signals independently. Usually, the information is superimposed onto the power signal using an external modulator. Recently, power converters have been used to generate pulses not just for power conversion but also for information transfer simultaneously. This approach represents a fundamental difference because it exploits the signal processing potential of Pulse Width Modulation (PWM), where for power conversion only the average pulse width is used, while the information is represented by the harmonics instead of being filtered out, as typically done in power electronics. The concept of embedding information into the switching ripple generated by a switched-mode power converter has recently been dubbed Talkative Power (TP), in this paper referred as Talkative Power Conversion (TPC). TPC technologies are reviewed in non-isolated and isolated converters in this paper. Potential applications include visible light communications, battery management systems, switching reluctance generators/motors, microgrids, and wireless electric vehicle charging stations. Finally, trending topics are identified.

This paper proposes and analyzes a two-stage dc-dc isolated converter for electric vehicle charging applications, where high efficiency over a wide range of battery voltages is required. The proposed conversion circuit comprises a first two-output isolation stage with CLLC resonant structure and a second two-input buck regulator. The transformer of the first stage is designed such that its two output voltages correspond, ideally, to the minimum and maximum expected voltage to be supplied to the battery. Then, the second stage combines the voltages provided by the previous isolation stage to regulate the output voltage of the whole converter. The first stage is always operated at resonance, with the only function of providing isolation and fixed conversion ratios with minimum losses, whereas the second stage allows output voltage regulation over a wide range of battery voltages. Overall, it is shown that the solution features high conversion efficiency over a wide range of output voltages. This paper comprehensively describes the solution, including modeling, analyses, design considerations for the main circuit components (e.g., magnetics, switches), and modulation choices. Experimental results are reported considering a converter module prototype rated $10\,\mathrm{k}\mathrm{W}$, input voltage $800\,\mathrm{V}$, and output range $250\,\mathrm{V}$ to $500\,\mathrm{V}$, employing silicon-carbide and gallium-nitride semiconductors.

The transformer leakage inductance is one of the limiting factors for pulse shape quality in high voltage pulsed power (HVPP) converters that are essential in applications such as cancer treatment, particle accelerators, and free electron lasers. Cone winding matrix (CWM) transformers are commonly used in HVPP converters as they offer low leakage inductance and high insulation distance. This paper proposes an improved Triple-2D (iT2D) leakage inductance model for CWM transformers. The iT2D model identifies three basic cross sections of CWM transformers and calculates their associated leakage inductance contributions. The paper proposes an accurate and compact analytical formula of the leakage inductance contribution resulting from the magnetic energy stored in between the magnetic cores. For cross sections with cone windings, an expression is presented that computes the leakage inductance per unit length of non-parallel windings. The iT2D model is verified with measurements and finite element simulations of three transformer prototypes. The analytical solutions used in the iT2D model ensure applicability to arbitrary geometric aspect ratios and designs. Furthermore, the iT2D model is rapidly executable enabling its time-efficient integration in converter optimisations.

DC circuit breakers are required to interrupt dc faults in multi-terminal HVDC (MTDC) grids. Consequently, their current limiting inductors can substantially impact the dynamic performance and stability of MTDC grids. However, the literature does not address the assessment and mitigation of dc breaker inductance impacts on the stability of an MTDC grid equipped with a power flow controller (PFC). To fill in this gap, this paper evaluates the effects of dc breaker inductance on the stability of a PFC-equipped MTDC grid. Furthermore, the paper expands the capability of the PFC via the development of a PFC-based damping controller to improve the dynamic performance of the MTDC grid and enhance its damping. First, a comprehensive small-signal model of the PFC-equipped MTDC grid is developed. Then, eigenvalue and frequency response analyses are employed to assess the dynamic performance and stability of the MTDC grid, considering the effects of breakers inductances, PFC and converter station control parameters, and network parameter uncertainty. Finally, time-domain simulations and hardware-in-the-loop real-time simulations are carried out to evaluate the performance of the proposed damping controller and verify the theoretical analysis.

Multilayer Ceramic Capacitors (MLCCs) are of paramount importance in electronics and ferroelectric Class II dielectrics enable outstanding energy-density values. However, the non-linear dielectric constant and associated low-frequency large-signal excitation losses of Class II MLCCs may cause critical overheating. A peak-charge based Steinmetz loss model entitled iGSE-CQ is known in literature and allows to accurately calculate MLCC low-frequency large-signal excitation losses under various operating conditions including biased and non-sinusoidal excitation voltage waveforms. Such a macroscopic iGSE-CQ model, however, is inherently limited to a specific MLCC, and in contrast to Steinmetz loss modeling for ferromagnetic inductor cores, the losses of other devices employing the same dielectric material cannot be predicted. Recent literature therefore proposed a microscopic and/or material specific MLCC Steinmetz Model entitled iGSE-CD which allows to calculate the losses of any MLCC of the same dielectric material based upon just a single set of Steinmetz parameters. However, due to the lack of information on the internal device geometry, the iGSE-CD could be verified only indirectly so far by means of a loss normalization based on the device capacitance and rated voltage. In this paper, we demonstrate the feasibility of a microscopic iGSE-CD MLCC loss model enabled by manufacturer data on the internal capacitor structure. The iGSE-CD is verified for two different MLCC series employing a conventional X7R dielectric and a novel Hiteca (with reduced non-linearity) Class II dielectric material with loss estimation error below $22\%$. This error results due to component tolerances and is acceptable, especially when compared to the loss calculation based on the datasheet information which can be off by up to a factor of ten. The analysis of the Hiteca dielectric reveals a frequency behavior different to the X7R material, and is discussed in the Appendix of this paper.

A novel single-stage LED driver for street lighting application is proposed in this article which combines a totem-pole boost PFC and a non-isolated LCCL resonant network. The converter offers several benefits, including: appropriate total harmonic distortion (THD) level and high power factor (PF) of the input current; reduced conduction losses and suppressed electromagnetic interference (EMI) thanks to its bridgeless structure; zero-voltage switching (ZVS) for the main switches and zero-current switching (ZCS) for rectifier diodes across the entire input voltage range and load conditions; a constant output current to an LED string load due to the LCCL network characteristic at the resonant frequency; and fixed-frequency operation via the main switches duty cycle for regulating the output current. The paper provides a detailed explanation of the proposed driver operating modes and theoretical analysis, as well as a comprehensive analysis of the impact of parameters on DC-link voltage level and main switches voltage stress. A design procedure is also presented. Experimental verification is demonstrated through a 100W prototype circuit operating at 200 kHz.

The fast switching of wide-bandgap (WBG) devices and the resulting harmonics in the switching waveforms can cause significant overvoltages in medium frequency transformers (MFTs). To enhance the reliability and lifetime of MFTs, fast and accurate models for these high frequency effects in the windings are necessary. The effects can be described using large multiconductor networks. However, computing the frequency-dependent parameters of such networks – namely the impedance and capacitance matrices – typically involves time-consuming finite element analysis (FEA), hindering the investigation of multiple designs in a reasonable timeframe. Therefore, this paper presents an analytical approach to compute impedance and capacitance matrices for the equivalent networks, focusing on an efficient algorithm to compute the capacitance matrix as well as an appropriate length scaling of the calculated per-unit-length matrices. Simulation and measurement results show that the proposed models can compute internal overvoltages more than 500 times faster than FEA, while predicting the maximum overvoltage with an error of less than $7 \%$. The individual validation of all presented submodels not only confirms the applicability to overvoltage modeling, but also demonstrates a potential use of the models in other areas of high-frequency modeling.

The 48 V voltage regulation modules (VRM) for microprocessors feature a high voltage transformation ratio, large current, and ultra-low voltage output. The solutions based on high-turns-ratio transformers are the most popular ones. However, these transformers often suffer from significant winding loss and large size issues, which are the main bottlenecks in improving efficiency and power density. This paper proposed a highly integrated planar transformer suitable for high-voltage-ratio VRMs with high current and ultra-low voltage output. The transformer integrates with the SRs and output capacitors and has a 1/10 turn on the secondary side, which can effectively reduce winding loss and improve power density. The winding length is determined by the size of the SRs and the output capacitors, resulting in a quite different design and optimization process from traditional transformers. The constraints of the transformer structure are analyzed and a flexible and compact structure is achieved on a 6-layer PCB. Based on the proposed transformer, a 40 V--1 V/200 A, 1 MHz LLC DCX is built. Experimental results show that the LLC DCX achieves a peak efficiency of 97% and a power density of 1394 W/in3, surpassing the state-of-the-art transformer-based solutions.

The DC-link capacitor represents a critical component in electric vehicle traction inverters, given that it constitutes the largest single volume within a traction inverter. The DC-link capacitance must be selected carefully, to ensure that the voltage ripple remains within defined limits, as this has a direct impact on the design of other components connected to the high voltage bus. Typical approaches attempt to reduce the required DC-link capacitance by increasing the pulse width modulation (PWM) switching frequency. However, this leads to a compromise as higher switching frequencies can cause additional losses, potentially necessitating a larger area for costly silicon carbide (SiC) semiconductors. In this contribution, optimized pulse patterns (OPPs) are proposed as a solution to improve the DC-link voltage ripple, allowing a reduction in capacitor size and a significant decrease in switching frequency compared to the standard Space-Vector PWM. The paper outlines the mathematical methods for simulating and designing the DC-link regarding voltage ripple and current stress. It compares the simulations for Space-Vector PWM and OPPs, leading to the development of two distinct capacitor designs. The theoretical 20% reduction in the volume of the DC-link capacitor is confirmed through experimental validation on a 250 kW machine test bench setup.

This paper presents the theoretical analysis and experimental validation of a harmonic-terminated high-efficiency and high-power microwave rectifier. The rectifier is designed utilizing a single-circuit gallium nitride (GaN) quasi-vertical Schottky barrier diode (SBD). Capitalizing on the strengths of wide bandgap, high mobility and high saturation velocity of the GaN, the SBD achieved a high breakdown voltage of 180 V and an ultra-low turn-on voltage of 0.23 V (at 1 A/cm$^{2}$). These characteristics enhance rectification performance across both high and low input power regions, making it suitable for wireless power transfer (WPT) applications. The optimized high-power microwave rectifier incorporates this advanced diode, featuring a wide input power range and high efficiency. The proposed rectifier structure includes a single-shunt self-developed SBD and topology with a harmonics compression network. It accomplishes a maximum RF-to-DC power conversion efficiency of 70.4% with an input power of 42 dBm (15.8 W) at 0.9 GHz. The highest efficient power handling ability is up to 20 W with an 18 dB (25–43 dBm) dynamic range achieving an efficiency exceeding 50%, demonstrating the high potential of high-power GaN SBDs for wireless high-power transfer for future microwave WPT applications.

Managing the thermal behavior of GaN devices under test (DUT) poses significant challenges during accelerated thermal cycling (ATC) tests, particularly due to the compact packaging of small GaN devices (e.g., QFN package) and the sharp rise in the device's $R_{\rm{DSon}}$ at high junction temperatures. This paper presents a framework for analyzing and modeling the thermal response performance of the ATC test setup and evaluating the impact of non-linear dissipated power on the GaN DUTs. It outlines the limitations of conventional thermal sensors in accurately estimating the DUT's junction temperature through case temperature measurements under ATC conditions. The analysis and modeling of the experimental junction temperature response function shows about 4 s time constant in the measurements using a thermistor placed near the DUT, highlighting the GaN DUT's susceptibility to thermal runaway under ATC conditions ($T_{\rm{j-max}}$ > 125 °C), where the thermal time constant significantly exceeds the DUT's thermal transient time. Consequently, an on-state resistance ($R_{\rm{DSon}}$)-based $T_{\rm{j}}$ estimation method is employed to monitor the $T_{\rm{j}}$ and control the thermal cycling window boundaries effectively. Experimental investigations of several e-mode GaN HEMTs under different ATC windows are conducted to validate the ATC testing framework. Moreover, the temperature coefficient of on-state resistance (α) is characterized and quantified - considering fully packaged individual GaN DUTs’ mechanical and electrical degradation mechanisms.

Fast and accurate switching loss models that can be used for different devices are crucial for optimization-based converter design. This paper proposes a novel data sheet based, fully analytical loss model for a SiC MOSFET and Schottky diode half-bridge including parasitics. In the model, nonlinear device characteristics are approximated by multi-step piecewise constants. Furthermore, a small number of assumptions are used to derive and to solve the approximated nonlinear differential equations for obtaining the switching losses. To evaluate the model, a new accuracy measure is proposed for a fair accuracy comparison with existing models. The proposed model is also comprehensively verified by double pulse tests using 5 SiC MOSFET (with different structures) and Schottky diode pairs from different manufacturers. The proposed fully analytical model exhibits on average the best accuracy with a high computational efficiency (less than 1 ms per operating point) compared to state-of-the-art analytical switching loss models, as validated by using both data sheet information and measured device characteristics.

With the increasing penetration of wind turbine (WT) systems with permanent magnet synchronous generators (PMSGs) into the power grids, the back-to-back converter (BTB) has become the key element interfacing wind sources and power grids. Compared to the grid-following voltage source converter (GFL-VSC), the grid-forming VSC (GFM-VSC) shows voltage and frequency support capabilities, which meets the requirement of grid codes for WT systems. Usually, the linear regulator is employed to realize the tracking of voltage and current of GFM-VSCs, but it has limitations of complex parameter design and dynamic performance. Recently, the model predictive control (MPC) is a promising alternative controller due to the easy adoption and fast control response. This paper proposes a novel MPC method for BTB to achieve grid-forming function. The model-based control concept of the MPC effectively overcomes the complex parameter-tuning process of the cascaded linear regulators. In addition, the overshoot in the step-response of the active power of GFM-VSCs during transient process is effectively improved by using a new multi-objective cost function. The reduced power overshoot is beneficial for fully utilizing the overload capacity of the converter, avoiding damage to semiconductor devices and causing system blocking. Finally, the simulation and experiments have confirmed the feasibility of the proposed MPC method.

The conventional TO-247-3 packages with single-sided cooling limit the thermal and electrical performances of discrete SiC MOSFET devices. In this paper, a double-sided cooling press-pack (PP) packaging approach for the discrete SiC MOSFET device is proposed to optimize its thermal and electrical performances. First, a double-sided cooling PP structure for the discrete SiC MOSFET devices is designed with a copper foam gate pin and an embedded fixture. Then, based on finite element simulations, the steady-state thermal and electrical performances of the discrete SiC MOSFET device with the double-sided cooling PP package are analyzed, and the parasitic inductance of the designed SiC MOSFET device is extracted by the ANSYS Q3D software. Finally, a prototype of the double-sided cooling PP SiC MOSFET device is fabricated, and test platforms are established to verify its performance. The research findings demonstrate that the designed double-sided cooling PP SiC MOSFET device can reduce thermal resistance and switching loss by 47.4 % and 42.3%, respectively.

This paper proposes a novel modulation scheme for a multilevel Dual Active Bridge (DAB) DC–DC converter with direct power transfer capability in PV applications. The proposed modulation scheme has the ability to shape the high-frequency current waveforms, leading to lower peak/RMS values of current over a wide range of PV voltages. In addition, the multi-level structure allows for the use of low-voltage devices with significantly smaller channel resistance. The power circuit topology is based on a current-fed half-bridge (CF-HB) converter, with a coupled inductor, which facilitates the direct power transfer, resulting in significantly lower conduction losses. In summary, the proposed topology tackles both the conduction and switching losses through a multi-faceted approach by using the novel modulation scheme, the multi-level structure, the direct power transfer, and the inherent soft-switching. Detailed mathematical analysis and extensive experimental results demonstrate the superior performance of the proposed converter.

This research paper presents a novel series of high-gain DC-DC converters developed explicitly to power High-Intensity Discharge (HID) lamps. The suggested configurations utilize Voltage Multiplier Cells (VMCs) and incorporate a diode to achieve ground separation. The inclusion of a diode improves voltage gains while ensuring compatibility with the requirements of HID lamps. The modified boost topology maintains a continuous input current and minimizes stress on the input filter capacitors. This study introduces the concepts of Small Signal Modelling and Bode diagrams in the context of controller design. Additionally, open-loop and closed-loop tests are conducted to observe and analyze steady-state and transient responses. The performance of the proposed topologies is analyzed under both ideal and non-ideal operating conditions. The simulation and experimental results are presented for comparison. The benefits of the proposed solutions are underscored by efficiency calculations and a comparative analysis with recently proposed topologies. The experimental findings provide empirical evidence supporting the theoretical conjectures, showcasing an efficiency of more than 93 % for a 60W prototype. Furthermore, these results affirm a strong concurrence among the simulation, experimental, and analytical approaches.

The reduction of the human environmental footprint can be achieved through the use of more efficient motors, such as synchronous reluctance motors (SynRMs). Known for their affordability, SynRMs are increasingly employed in sensorless AC drives. This paper presents a critical comparison of sensorless algorithms based on two nonlinear Kalman Filters (Unscented and Extended). The objective is to highlight the theoretical and practical advantages and drawbacks of each method when applied to the speed control of a SynRM, culminating in a definitive decision on the best choice. The magnetic model of the SynRM is much more nonlinear than that of induction motors, which are predominantly addressed in existing literature. This study aims to fill the gap by answering the question: “Is the extended Kalman filter still the best choice even in the case of nonlinear electric motors?” The answer comes through a large batch of experiments, including speed and load torque tests, zero-speed standstill starts, parameter sensitivity, and evaluation of computational burdens for both Kalman filter algorithms.

DC microgrid systems are increasingly utilized in power systems, and the significance of solid-state circuit breakers (SSCB) is paramount due to the absence of zero-crossing current in DC systems. However, one of the concerns in a DC microgrid is proposing and implementing a new algorithm due to safety concerns and system stability. Properly coordinating a DC microgrid is one of these challenges. Moreover, protecting the system from unpredictable transient overshoot plays a significant role in system stability and SSCB performance. Consequently, the design of a virtual test platform for monitoring the system's behavior in challenging situations holds significant importance. To address these matters, this paper presents an examination of a DC microgrid using a novel, easy-to-implement, and cost-effective controller hardware-in-the-loop (CHIL) test platform. This platform utilizes MATLAB/Simulink software as a simulator and proposes a new communication path between the simulator and real-world controllers. Additionally, a new method to control the system in overshoot situations is proposed. To demonstrate the effectiveness of the proposed CHIL platform, three short-circuit CHIL tests are performed for load#1 to load#3 at 430 A, 300 A, and 180 A fault currents, respectively. To investigate the designed algorithm protection, a complex protection experiment was conducted to evaluate the performance of the designed algorithm under multiple transient overshoot conditions in the current. The extracted CHIL results are also presented as the validation of proposed algorithm.

Heat sinks are a fundamental component of power electronics converters, so it is important to have a reliable method to study and optimize their size. Thermal analysis of heat sinks can be a complex problem as it involves different heat transfer mechanisms, and it is often necessary to use finite element simulations to obtain accurate results. However, these simulations, being very slow, are relegated to the validation process. This paper proposes a thermal model of heat sinks based on artificial neural networks. The model, unlike previous state-of-the-art models that only obtain the average temperature of the heat sink, is able to obtain a thermal map of the heat sink surface, as if it were an image, by using convolutional layers. The main advantage of this approach is that using these convolutional layers, the model is able to efficiently process how the elements are distributed on the heat sink. This model, valid for heat sinks of very different sizes in both laminar and turbulent flow, has an error of less than 1.5% and is 1500 times faster than finite element simulations, so it can be easily used in brute-force optimization processes, where many different designs need to be analyzed.

This paper presents a novel reduced-order modeling approach for efficient modeling and dynamic stability analysis of a utility-scale hybrid grid-tied system comprising a photovoltaic (PV) array, wind turbine (WT), battery energy storage system (BESS) and the associated power electronic converters and control systems. Utilizing the singular perturbation analysis, the time-domain nonlinear model (TDNLM) of the grid-tied hybrid PV-WT-BESS system is linearized to construct the linearized state-space full-order model (LSSFOM). Categorizing the dynamics of the LSSFOM into fast and slow states based on their weighted dynamics utilizing the participation factor analysis and the residue-based method, the model is further reduced to the linearized state-space reduced-order model (LSSROM), focusing on dominant slow-dynamic states that characterize the overall system dynamics. The LSSROM is employed to investigate dc and ac dynamic interactions under various operational conditions, including all PV, WT, and BESS operating regions and grid stiffness conditions. The proposed reduction approach reduces the computational burden with simplicity and efficiency, facilitating the development of reliable reduced-order models capturing the essential features of the original detailed full-order model with a high degree of acceptable accuracy for dynamic and stability analyses across diverse operating conditions while ensuring versatility. Detailed offline and real-time simulation results validate the analytical results, demonstrating the efficiency of the proposed approach across different operational scenarios.

Average-value models (AVMs) of voltage-source converters (VSCs) are widely used as numerically efficient alternatives to their discrete switching models in electromagnetic transient (EMT) simulations. Recently, a so-called directly-interfaced AVM (DI-AVM) has been developed for VSCs, permitting large simulation time steps favorable for system-level offline and/or real-time studies. Although enabling large step sizes, the conductance/resistance matrix of the DI-AVM is time-varying and needs to be calculated at every simulation time step, which requires additional computational resources. This paper proposes a constant-parameter DI-AVM (CP-DI-AVM) for more efficient simulations of VSC-based power-electronic systems that does not require re-calculation of the network conductance matrix in EMT simulators. This is achieved by using a numerical approximation that only slightly reduces the solution accuracy. The performance of the proposed CP-DI-AVM is demonstrated on a large-scale VSC-based energy conversion system implemented in PSCAD/EMTDC. The proposed CP-DI-AVM is shown to have numerical advantages over the prior DI-AVM and the conventional AVMs of VSCs.

The integration of dc microgrids (MGs) into distribution networks offers a promising solution to address the growing demand for electric energy by facilitating the incorporation of renewable energy sources and energy storage systems. To ensure sustained and reliable operation, dc MGs are commonly linked to utility grids through interlinking converters. However, with the increasing adoption of small-scale dc MGs for residential and commercial applications, the traditional approach of using a dedicated converter for each MG can significantly increase system size and cost. This paper proposes a single-stage non-isolated multiport converter (MPC) to interface the three-phase ac grid with 400 V dc MGs. The MPC enables direct power sharing between dc MGs, minimizes the dependence on the ac grid, and enhances the efficiency and power density of the power electronic interface compared to using multiple two-port converters. The motivations for the proposed converter include its single-stage power conversion among different ports, potentially leading to enhanced efficiency and power density. Furthermore, the absence of bulky intermediate dc-link capacitors and transformers in the proposed topology contributes to improved power density and reduced costs. Although designed for 400 V dc MGs in this study, the proposed MPC boasts buck-boost capability and bidirectional power flow at all ports, independent of the dc ports' voltage, providing the flexibility to directly interface with a wide range of dc systems. The performance of the converter is assessed through experimental tests under various operating conditions.

Power quality is critical in ensuring the efficient operation of electrical systems, and Unified Power Quality Conditioners with Distributed Generation (UPQC-DG) systems play a vital role in mitigating power quality issues such as voltage sags, swells, harmonics, and flicker. Proportional-integral (PI) control UPQC-DG systems are crucial for maintaining power quality by stabilizing the DC link voltage, which is also essential for the seamless integration of distributed generation into the power grid. Effective PI control ensures minimal voltage fluctuations and rapid response to disturbances, thereby enhancing overall system reliability and efficiency. However, traditional PI tuning methods, like the Ziegler-Nichols (ZN) approach, often fail to provide optimal performance under dynamic conditions in such complex converters. To address these limitations, this paper presents an innovative approach for real-time tuning of PI controllers in UPQC-DG systems using Particle Swarm Optimization (PSO). The primary objective is to dynamically optimize the PI controller parameters to enhance the stability and performance of the DC link voltage under varying operational conditions. The proposed method was validated in a real-time simulation environment using the OPAL-RT 4512 platform. The results demonstrate the PSO-based method's superior ability to reduce steady-state errors and enhance dynamic response as well. This study underscores the potential of PSO for real-time adaptive control, providing a robust solution for maintaining high power quality in UPQC-DG systems and improving the stability and reliability of distributed generation systems.

In the realm of electric mobility, fast chargers for electric vehicles (EVs) play a critical role in mitigating range anxiety while driving. The converter in these chargers usually has a load profile consisting of a high-current pulse to swiftly recharge the EV battery, followed by a cooling-off phase when the charging process is over. This pattern results in thermal cycles on the devices resulting in mechanical fatigue that leads to gradual deterioration of the power electronic components. Consequently, evaluating the power electronic converters reliability is critical to facilitating fast EV charging. This paper focuses on the reliability analysis of the phase-shifted full-bridge DC/DC converter within EV fast chargers, with a specific emphasis on the battery charging profile. The primary objective is to demonstrate how the charger load characteristics and number of charging sessions influence device reliability and, consequently, overall system reliability. Additionally, the investigation explores the effects of altering devices heatsinks and current ratings on system reliability. It was observed that in worst-case scenarios, increasing devices current rates extended the system lifetime from 0.7 to about 23 years, with $3\,\text{p.u.}$ ratings achieving 10.8 years, meeting industry targets, while reducing heatsink thermal resistance improves that to around 2 years.

Due to the ever-increasing switching speeds of wide band gap (WBG) devices, the high-frequency behavior of magnetic components, such as medium-frequency transformers, is becoming increasingly significant. To describe this complex high-frequency behavior, large multiconductor networks are commonly employed. The frequency-dependent parameters of these networks are typically represented as matrices. However, accurately calculating these matrices often necessitates time-consuming finite element analysis (FEA), which significantly limits the investigation of various geometries within a practical timeframe. This paper addresses this problem by proposing a model based on analytical formulations for the frequency-dependent resistance and inductance matrices of transformers with litz wire windings. The model is experimentally verified showing good agreement to the measurements over a wide frequency range. Compared to FEA only a marginal deviation of less than 2% is noticeable, whereas the calculation is more than 200 times faster.

The bus conversion system in the hybrid AC/DC grid is usually composed of a three-phase interlinking converter and a DC-side input filter. The impedance interaction between the converter and the input filter may cause instability of the DC-link voltage. The previously proposed stabilization methods either require additional hardware or significantly impact the dynamic performance. Therefore, this paper presents a parallel virtual impedance regulator (PVIR), which adds desired virtual impedance in parallel with the input impedance of the converter. The proposed PVIR can precisely modify the impedance within the specific frequency range to minimize the impact on the system dynamics. The concept and detailed design procedure with the redundant design of the PVIR are introduced. The effect of the PVIR injection position is discussed. Finally, the experiment validates the effectiveness of the proposed PVIR.

In this paper, a single-stage buck-boost differential inverter is optimally designed for applications with varying input DC voltage (e.g., photovoltaics and fuel cell systems). The designed inverter has multiple functionalities, including power decoupling and AC output filtering, and it can operate with a wide DC voltage range without adding extra power conversion stages or filters. Hence, it is naturally compact and highly efficient. To fully exploit its benefits, the proposed inverter operating principle and mathematical model were first developed to form the foundation of an optimal design. The criteria for selecting the inverter's key components have been presented. This ensures that the developed inverter meets the aforementioned functional requirements without being overly sized. A digital design procedure based on artificial neural networks is followed for further multiple objective optimization, targeting high efficiency, high power density and low cost. A 1.8kW prototype of the inverter was fabricated through the digital design. The inverter's operating functionality with varying DC voltage, power decoupling, and filtering was demonstrated by both simulation studies and experimental tests on the prototype. The accuracy of the optimal design was also validated.

This article provides a comprehensive overview of the state of the art in the field of permanent magnet biased inductors, (PMBIs). The theoretical benefits of PMBIs, operating in DC applications, were identified decades ago, in the late 1950’s. Compared with a non-biased inductor, a 100% linear biased PMBI, can achieve the same inductance and saturation current, while requiring only half of the core's cross-sectional area or half the number of turns. In practicality, achieving 100% biasing without introducing additional losses, or detrimental conditions for the permanent magnet's lifetime, becomes an important challenge and the development and achievements of PMBIs have been evolving until present days. Therefore, this overview paper, first introduces the basic background knowledge required for the development of PMBIs, including an overview of the design benefits of biasing, the possible design strategies, additional benefits and possibilities of over-biasing, and a brief introduction to permanent magnets, PMs. The historical evolution of the different biasing techniques, and the employed core and PM topologies, are analyzed and evaluated. The different physical prototype implementations found in the literature, and their operating characteristics, achievements, and limitations, are compiled and evaluated. Finally, the present challenges of PMBI implementation, and the future perspectives towards optimized development are summarized.

This paper proposes a process for measuring the rated power electrical characteristics of inductive power transfer (IPT) coupling pads in limited laboratory environments through topology reconfiguration. Among the components of IPT systems, the coupling pad is responsible for the main losses in the converter. Moreover, coupling pads have nonlinear characteristics that depend on various factors, such as the number of coil turns, the diameter, the permeability of the magnetic material, and the amount of aluminum. Therefore, verifying the operation is necessary when applying various position and control algorithms after configuring an IPT system. The input/output characteristics of the IPT system are mainly determined by the coupling pad and the employed compensation topology. Verifying the operation of the coupling pad becomes challenging when the IPT application's required input/output characteristics exceed the experimental voltage range in laboratory environments. The same electrical stress is applied to the coupling pad through topology reconfiguration and resonance component tuning, and the input/output characteristics can be flexibly changed to present a guideline that can be tested in a laboratory environment. A 3-resonance component circuit allows for modeling various compensation topologies. The same electrical and heating stress are verified through a 3.3-kW experimental prototype.

The increasing popularity of Electric Vehicles (EVs) can be attributed to recent advancements in highly efficient power conversion technology, as well as a desire to reduce reliance on fossil fuels. As a result, bidirectional DC-DC converters have gained significant interest and importance in the field of electric vehicle applications. This paper introduces an enhanced DC-DC converter, the Bidirectional Dual-Input Single-Output (BDISO) converter for the Electrical Vehicle application, which combines multiple energy sources for efficient power delivery to a load. The converter offers versatile operational modes and employs a Passivity-Based Control (PBC) strategy for stable closed-loop control. A mathematical model is developed and analyzed to understand its behavior. In addition, rigorous evaluations of reliability and efficiency demonstrate robust performance and high operational efficiency across various conditions in comparison with exciting systems. Finally, the proposed converter with its controller is validated through simulation and experimental results.

The recent transformation of the energy sector brings new challenges in areas such as supply security, efficiency, and reliability. Especially the increase of decentralized power plants leads to a more complex energy system and an increasing complexity. This requires expansion and digitization of the power grid as well as an initiative-taking operation of the grid operator. To investigate such complex systems and its phenomena, modern development methods such as real-time simulation or digital twins (DT) can be used. In this approach a digital replica of the real-world system, a grid section, is developed, which can represent or predict the behavior of the real distribution grid. For this, a model of the real-world system is derived and implemented in a co-simulation environment, in which it receives data via an analyzer or measurement system from the grid model. This paper focuses on the development of the digital twin of a testing grid and a grid analyzer for the measurement. With the digital twin of the testing grid, a first approach is achieved in a real-time capable environment showing the functionalities and interactions of a digital twin. Subsequently the development of the digital twin model is explained, and the results are discussed.

Designing power electronics converters for harsh environments is challenging due to the absence of components' performance under harsh conditions, the frequent transition and data-passing among various software, and the time-consuming and computationally heavy work flow. This paper promotes using design automation to address the aforementioned design challenges. The implementations include public-accessible component databases, automated co-action among circuit simulators and finite element simulations to perform electrical, electromagnetic and thermal co-design, and finally an exclusion-based work flow with hierarchical computation to reduce computational load. The theorized framework is exemplified on designing a real world 175 °C 1.5 kW Three-level Neutral-point-clamped dc-dc converter. A database containing the high-temperature characteristics of SiC MOSFETs and ferrites is established and shared through a web application with graphical user interface. In 310 min, the program, which includes computationally heavy 3D finite element simulation, delivers design output after evaluating the converter's electrical, electromagnetic and thermal performance under 10 million parameter sets. Finally, a 1.5 kW dc-dc converter prototype is built and tested in 175 °C ambient temperature to verify the quality of the design output.