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In this study, we investigate the effects of intentional crosstalk noise on modern Multi-Processor System-on-Chips (MPSoCs). We demonstrate the potential for an adversary to inject false data into the communication network of the MPSoC, thereby creating intentional crosstalk scenarios that increase the likelihood of bit errors in other users’ data. This is achieved through a pre-attack reconnaissance phase in which the attacker determines the size of the MPSoC’s communication links. Based on this information, the attacker then issues false packets into the MPSoC’s network to intentionally corrupt users’ data. Our evaluations confirm that the attack can have serious consequences, altering the on-chip communication system of MPSoCs. Additionally, we propose a multi-layer defense mechanism that ensures the proper functioning of the MPSoC in the presence of both benign and malicious crosstalk scenarios. Our experimental results confirm the effectiveness of our proposed method in addressing at least 88% of the crosstalk situations with minimal power and performance overhead compared to alternative solutions.

The die-stacking structure of 3D network-on-chips (3D NoC) leads to high power density and unequal thermal conductance between different layers, which results in low reliability and performance degradation of 3D NoCs. Congestion-aware adaptive routing, which is capable of balancing the network’s traffic load, can alleviate congestion and thermal problems so as to improve the performance of the network. In this study, we propose a traffic- and thermal-aware Q-routing algorithm (TTQR) based on Q-learning, a reinforcement learning method. The proposed algorithm saves the local traffic status and the global temperature information to the Q1-table and Q2-table, respectively. The values of two tables are updated by the packet header and saved in a small size, which saves the hardware overhead. Based on the ratio of the Q1-value to the Q2-value corresponding to each direction, the packet’s output port is selected. As a result, packets are transferred to the chosen path to alleviate thermal problems and achieve more balanced inter-layer traffic. Through the Access Noxim simulation platform, we compare the proposed routing algorithm with the TAAR routing algorithm. According to experimental results using synthetic traffic patterns, our proposed methods outperform the TAAR routing algorithm by an average of 63.6% and 41.4% in average latency and throughput, respectively.

Three-Dimensional (3D) Network-on-Chip (NoC) architectures being the combination of NoC and 3D die stacking chip integration technology are more prone to faults that might occur with ageing, low supply voltage or physical damage of the chip. Being the heart of NoC, the router is known for consuming significantly high power. With an on-chip testability feature for faults, the amount of power consumed increases linearly with the addition of logical components. This paper, proposes a power optimized Built-In Self-Test (BIST) capable 7-port router architecture for 3D NoC by considering Marching Memory Through Type for buffer design and Cellular Automata Rule 45 for test sequence generation. The power report generated for the proposed design has been compared against that of the conventional router without BIST capability and widely used Linear Feedback Shift Register based BIST capable router architectures and further a constructive discussion in this paper, states the advantages of the proposed design in comparison to its analogues.

In the paper we describe F-medians searching algorithm for Three-dimensional (3D) Network-on-Chip (NoC) design. Modern 3D NoC development is complex and complicated task. Developer should solve different problems: Intellectual Property (IP) blocks placement on the die, organization of vertical links between dies in the 3D stack, energy consumption limitation, system performance improvement. We consider approaches for placement vertical links on the die and suggest a new methods that are based on the P-median problem.