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Arithmetic circuits such as adders are fundamental components in implementing image processing applications. Since these applications are error-tolerant, the adders can be approximated to improve their PDP (Power-Delay-Product) metric while maintaining accuracy within tolerance limits. This paper proposes a segmentation technique to design ternary approximate adders, where the entire adder chain is split into segments, with the intent to reduce the delay. Next, for applications that require tunable accuracy, we incorporate a reconfiguration technique in the segmented approximate adders, using a divide-and-conquer methodology that dynamically optimizes the approximate adder’s accuracy, leading to efficient computation. Also, an algorithm was proposed to compute accuracy and hardware complexity in an N-trit accuracy reconfigurable adder. The proposed methodology was validated using an approximate 6-trit adder on its power consumption and delay performance metrics. Compared with the best design in literature, the proposed approximate 6-trit adder exhibits 63% lesser power consumption and 69% lesser delay. The proposed approximate 6-trit adder accuracy was progressively enhanced through the reconfigurable method. After a few reconfiguration stages, the proposed adder matched the accuracy of an exact 6-trit adder while achieving an improved power-delay product (PDP). Finally, the proposed 6-trit adders were validated by using them in the image-blending application.

Implementation of Convolutional Neural Networks (CNNs) on edge devices require reduction in computational complexity. Leveraging optimization techniques or approximate computing techniques can reduce the overhead associated with hardware implementation. In this paper, we propose a modular pipelined Feedforward CNN Hardware Accelerator (FHA) and a novel Approximate Feedforward CNN Hardware Accelerator (AFHA). The AFHA design is achieved through the incorporation of hardware pruning and Approximate Multiply Accumulate (AMAC) units. Our proposed architectures are validated for functionality through an image classification application, utilising the popular MNIST dataset for 8-bit, 16-bit and 32-bit operational word size. Performance analysis of our proposed architectures show that the 32-bit FHA consumes 307.04pJ of energy while achieving acceleration of 76.91x. AFHA attains an acceleration of 120.69x with an energy consumption of 295.85pJ. Similarly, the 16-bit and 8-bit architectures demonstrate substantial acceleration while significantly reducing power consumption. The performance of our proposed architectures demonstrates significant acceleration and reduced power consumption compared to popular edge machine learning framework - TinyML TensorFlow Lite. FHA achieves a significant accuracy improvement of 6.2% along with a speedup of 1.07x and AFHA achieves accuracy enhancement of 4.3% and an impressive speedup of 1.42x.

The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this study, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HAs) and full adders (A-FAs), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), Carry Select Adder (CSLA), and Clock Gating Technique. The proposed multipliers are implemented in Verilog HDL and simulated on the Xilinx VIVADO 2021.2 design tool, with the target platform being the Artix-7 AC701 FPGA. The results found that the power dissipation change is 13%, the delay change is 4.7%, and the area change is 15% for the 16-bit unsigned approximate multiplier. For the 16-bit signed approximate multiplier, the power change is 18.81%, the delay change is 3.57%, and the area change is 14.29% using inexact and exact adders and the clock gating technique with CSA as the final partial product summer. Clock-gating 16-bit multiplier RED decreases when compared to approximate adder usage alone in the multiplier. The proposed multipliers are useful in error-tolerant applications such as digital signal processing, image fusion, image blending, smoothing, and sharpening to produce high-quality images at high speed and with low power consumption.

Efficiency, low-power consumption, and real-time processing in embedded machine learning implementations are critical, particularly for models deployed in environments with large-scale data processing and resource-constrained environments. This paper investigates the application of approximate computing techniques as a viable solution to reduce computational complexity and optimize machine learning models, focusing on two widely used supervised machine learning models: k-nearest neighbors (KNN) and support vector machines (SVM). Although many studies compare machine learning classification techniques, the combined use of optimization strategies remains underexplored. Specifically, the combined utilization of feature selection, sampling, quantization, precision scaling, and relaxation methods for the purpose of optimizing and acquiring training and validation data is underexplored, particularly within the context of medical diagnosis datasets. In this paper, we propose a framework that uses data-level approximate computing techniques, including by diverse sampling strategies, precision scaling, quantization, and feature selection methods, to evaluate the impact of these techniques on the computational efficiency and accuracy of KNN and SVM models. Experimental results demonstrate that with careful application of approximate computing strategies, especially in critical applications such as medical diagnosis, it is possible to achieve considerable gains in efficiency while maintaining acceptable levels of accuracy. The combined application of these methods by selecting 3 features and quantizing the data values to 8 levels, then applying random sampling with 30% reductions and scaling the precision at 5 bits resulted in reductions of 87.5% in computation, 76.9% in memory usage, and 17% in delay, without any degradation in accuracy, as validated by tenfold cross-validation, Training Data validation, and full dataset validation. This study confirms the potential of approximate computing to optimize machine learning workflows, making it particularly suitable for applications with limited computational resources. The source code is publicly available online https://github.com/AyadMDalloo/DatalvlAxC.

Approximate computing is a new design concept that causes a trade-off between circuitry performance and accuracy. The approximate circuits are more useful in error-resilient applications, like image processing. This paper introduces a new imprecise 4:2 compressor with 12 transistors. The presented compressor exhibits low power consumption and provides full-swing outputs, due to the utilization of gate diffusion input and dynamic threshold techniques. The implementation of this compressor using a 16 nm carbon nanotube field-effect transistor (CNTFET) technology yields a minimum area. According to the simulation results, the suggested imprecise 4:2 compressor shows a significant reduction in power consumption and power-delay-product (PDP) compared to the precise 4:2 compressor, with a reduction of 95.18% and 95.27%, respectively. Also, the compressor is evaluated regarding the approximate figure of merits like error rate, mean error distance, and normalized mean error distance. The simulation results affirm the priority of the suggested circuit, especially in digital signal processing.

The increasing computational demands of emerging deep neural networks (DNNs) are fueled by their extensive computation intensity across various tasks, placing a significant strain on resources. This paper introduces DART, an adaptive microarchitecture that enhances area, power, and energy efficiency of DNN accelerators through approximated computations and decomposition, while preserving accuracy. DART improves DNN efficiency by leveraging adaptive resource allocation and simultaneous multi-threading (SMT). It exploits two prominent attributes of DNNs: resiliency and sparsity, of both magnitude and bit-level. Our microarchitecture decomposes the Multiply-and-Accumulate (MAC) into fine-grained elementary computational resources. Additionally, DART employs an approximate representation that leverages dynamic and flexible allocation of decomposed computational resources through SMT (Simultaneous Multi-Threading), thereby enhancing resource utilization and optimizing power consumption. We further improve efficiency by introducing a new Temporal SMT (tSMT) technique, which suggests processing computations from temporally adjacent threads by expanding the computational time window for resource allocation. Our simulation analysis, using a systolic array accelerator as a case study, indicates that DART can achieve more than 30% reduction in area and power, with an accuracy degradation of less than 1% in state-of-the-art DNNs in vision and natural language processing (NLP) tasks, compared to conventional processing elements (PEs) using 8-bit integer MAC units.

Many weight quantization approaches were explored to save the communication bandwidth between the clients and the server in federated learning using high-end computing machines. However, there is a lack of weight quantization research for online federated learning using TinyML devices which are restricted by the mini-batch size, the neural network size, and the communication method due to their severe hardware resource constraints and power budgets. We name Tiny Online Federated Learning (TinyOFL) for online federated learning using TinyML devices in the Internet of Things (IoT). This paper performs a comprehensive analysis of the effects of weight quantization in TinyOFL in terms of accuracy, stability, overfitting, communication efficiency, energy consumption, and delivery time, and extracts practical guidelines on how to apply the weight quantization to TinyOFL. Our analysis is supported by a TinyOFL case study with three Arduino Portenta H7 boards running federated learning clients for a keyword spotting task. Our findings include that in TinyOFL, a more aggressive weight quantization can be allowed than in online learning without FL, without affecting the accuracy thanks to TinyOFL’s quasi-batch training property. For example, using 7-bit weights achieved the equivalent accuracy to 32-bit floating point weights, while saving communication bandwidth by $4.6 \times $ . Overfitting by increasing network width rarely occurs in TinyOFL, but may occur if strong weight quantization is applied. The experiments also showed that there is a design space for TinyOFL applications by compensating for the accuracy loss due to weight quantization with an increase of the neural network size.

Multicore systems are utilized in a wide range of applications, from embedded systems to high-performance applications. Controlling power consumption while maximizing performance under the Thermal Design Power (TDP) becomes increasingly important when power density emerges as the key restriction for multicore systems. Dynamic voltage-frequency scaling (DVFS) approaches have been effective in dynamically power control and are commercially accessible. We propose a novel approach to improve the performance of multicore systems by utilizing configurable approximate Arithmetic units. The proposed system includes a machine learning-based framework for online power regulation and quality monitoring of application output. This framework dynamically adjusts the frequency and precision of the Arithmetic units to maximize performance while considering TDP constraints and the desired output quality. The experimental results demonstrate the effectiveness of the proposed approach. Using a floating point approximate Arithmetic Logic Unit (ALU) with three distinct configurations in each core, the multicore system can execute approximable applications up to 19% faster than a precise multicore system, while operating within the same TDP limit.

Approximate computing techniques, such as precision tuning, are widely recognized as key enablers for the next generation of computing systems, where computation quality metrics play an important role. In precision tuning, a trade-off between the accuracy of computations and latency (and/or energy) is established, but identifying the opportunities for applying this approximate computing technique is often challenging. In this article, we compare two different approaches — worst-case static annotation and profile-guided annotation — and their implications when used in a precision tuning framework. To ensure a fair comparison, we implement the profile-guided approach in an existing tool, TAFFO, and experimentally compare it to the original static approach used by the tool. We validate our considerations using the well-known PolyBench/C benchmark suite, and two real-world application case studies. Our findings demonstrate that the profile-guided approach, fed with reasonable profiling data, in addition to needing less expertise to employ, delivers comparable speedup and better accuracy than the static approach.

Image dehazing is a crucial task in the early stages of real-time image processing pipelines used in applications such as surveillance and advance driver assistance systems. Dehazing algorithms mitigate the spatially selective degradation of image details caused by natural phenomenon such as fog and sandstorms. The problem is exacerbated in the presence of color cast which can affect the color-sensitive processing in the downstream tasks. In order to correct these two aberrations, we have proposed a light-weight algorithm which is not only quantitively more effective than the state-of-the-art works but also uses minimal computational resources. Specifically, it has been proposed to tackle both aforementioned problems by processing luminance and chrominance channels separately through a custom resource-efficient colorspace transform. Moreover, it has been proposed to employ online calculation of the relevant video stream statistics to estimate the degradation model over several temporally adjacent frames. This approach not only reduces the hardware resource utilization when implemented inside the video processing pipeline but also reduces the flicker effect observed when frames are processed individually. It has been demonstrated through quantitative analysis on standard datasets that the proposed approach either works at par or better than the reference works in terms of image quality metrics. Furthermore, the proposed framework has been developed as a real-time video processing system on an FPGA platform. The synthesis results of this implementation suggest that the proposed framework achieves this performance using minimal logic resources.

Deep neural networks (DNNs) are a type of artificial intelligence models that are inspired by the structure and function of the human brain, designed to process and learn from large amounts of data, making them particularly well-suited for tasks such as image and speech recognition. However, applications of DNNs are experiencing emerging growth due to the deployment of specialized accelerators such as the Google’s Tensor Processing Units (TPUs). In large-scale deployments, the energy efficiency of such accelerators may become a critical concern. In the voltage overscaling (VOS) technique, the operating voltage of the system is scaled down beyond the nominal operating voltage, which increases the energy efficiency and lifetime of digital circuits. The VOS technique is usually performed without changing the frequency resulting in timing errors. However, some applications such as multimedia processing, including DNNs, have intrinsic resilience against errors and noise. In this paper, we exploit the inherent resilience of DNNs to propose a quality-aware voltage overscaling framework for TPUs, named X-TPU, which offers higher energy efficiency and lifetime compared to conventional TPUs. The X-TPU framework is composed of two main parts, a modified TPU architecture that supports a runtime voltage overscaling, and a statistical error modeling-based algorithm to determine the voltage of neurons such that the output quality is retained above a given user-defined quality threshold. We synthesized a single-neuron architecture using a 15-nm FinFET technology under various operating voltage levels. Then, we extracted different statistical error models for a neuron corresponding to those voltage levels. Using these models and the proposed algorithm, we determined the appropriate voltage of each neuron (the voltage level of each column of the X-TPU). Results show that running a DNN on X-TPU can achieve 32% energy saving for only 0.6% accuracy loss.

Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor and error compensation. The probability-optimized compressor is customized for partial product matrix (PPM) of signed operands, which gets the optimal logic circuit after probabilistic analysis and optimization. At the same time, we explored the PPM truncation method, found out the impact of different partial product (PP) truncation numbers on circuit benefit and error, and achieved a more ideal performance-error tradeoff through a reasonable error compensation method. In the optimal case of 8 bits, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. We employed the proposed approximate multiplier in the vector systolic array as the processing element (PE). Under the VGG-16 evaluation, the proposed accelerator achieves performance improvement of energy efficiency $1.96\times $ , while the error loss was only 0.95%.

Convolution is the inner product of the neighborhood signal and weights and plays a fundamental role in image processing; thus, acceleration of convolution is essential. Among convolutions, variable-weighted convolution is used in adaptive filters and edge-preserving smoothing to realize various applications. Some weights are replaced with lookup tables (LUTs) to accelerate these filters. LUT reference is a classical acceleration method. However, the difference between the growth rate in computing speed and memory I/O speed has limited the scope of utilization of LUT references. Speedup would be possible if registers could be used as LUTs, but their small size makes them difficult to utilize. Therefore, this study proposes a downsampling method to fit LUTs into SIMD registers, which are relatively large and an efficient reference method for register-LUTs. Experimental results show that the proposed method can reproduce an accuracy in PSNR of 65.52 (+25.11) dB, while a simple full-size LUT in the register size can only reproduce 40.41 dB. Using a wider register width, the PSNR was 78.63 (+38.22) dB with AVX-512 and 84.5 (+44.09) dB with bfloat16. The fastest proposed method was on average 4.82/3.72 times faster than direct vector computing, 2.99/3.10 times faster than vector addressing, and 3.79/7.80 times faster than scalar addressing on the AVX2/AVX-512 computers while exceeding the display limit of 60 dB for 8-bit displays. Taking into account these speed/accuracy trade-offs, the performance of the proposed method was superior. This paper shows that LUT references can be realized with small SIMD registers in convolution. The proposed method is expected to be extended to adaptive filters, convolutional neural networks, and other image processing applications by accelerating the approximation with this register-LUT. Our code is available at https://fukushimalab.github.io/registerLUT4conv/.

In Electrical Impedance Tomography, the ill-posed nature of the inverse problem and the interaction between the electric current and objects cause poor spatial resolution and blurring in the reconstructed images. This study proposes a numerical method, called the voltage-dependent point-spread function, which depends on the initial setting of the environment, such as voltage, conductivity, permeability, and frequency, to overcome the above problems. When the object layout is convoluted with a point spread function, the Electrical Impedance Tomography image can be reconstructed regardless of the conditions in forward and inverse problems, which is suitable for applications requiring big data, such as deep learning or machine learning. The object’s size in the Electrical Impedance Tomography image can be reconstructed to approximately the real size by deconvolution with a point-spread function. The proposed method was validated using conventional methods through simulations and experimental experiments. The results demonstrated the feasibility and applicability of this method in clinical practice.

Approximate computing is a technique that sacrifices the accuracy of the result for an advantage in terms of power, area, and speed. It is useful for error-tolerant applications such as image and video processing. Many approximate arithmetic circuits can be devised using approximate versions of the basic binary full adder that simply adds three bits to generate carry and sum. Therefore, the approximate full adder has been the subject of extensive investigation in recent years. In this paper we present a comprehensive analysis of approximate full adders, by synthesizing in a FinFET 14 nm technology the whole set of possible designs, achievable by modifying one or more entries of the full adder truth-table. Our exhaustive analysis shows that only a few out of the many thousands of synthesized circuits perform reasonably well as approximate full adders. Our analysis re-discovers the approximate full adders already proposed in the literature and identifies some new ones. Examples of using the newly discovered approximate full adders in typical error resilient applications are provided, showing the performance and the usefulness of approximate arithmetic circuit designs in the real-world.

The unprecedented progress in computational technologies led to a substantial proliferation of artificial intelligence applications, notably in the era of big data and IoT devices. In the face of exponential data growth and complex computations, conventional computing encounters substantial obstacles pertaining to energy efficiency, computational speed, and area. Due to the diminishing advantages of technology scaling and increased demands from computing workloads, novel design techniques are required to increase performance and decrease power consumption. Approximate computing, nowadays considered a promising paradigm, achieves considerable improvements in overhead cost reduction (i.e., energy, area, and latency) at the expense of a modest (i.e., still acceptable) deterioration in application accuracy. Therefore, approximate computing at different levels (Data, Circuit, Architecture, and Software) has been attracted by the research and industrial communities. This paper presents a comprehensive review of the major research areas of different levels of approximate computing by exploring their underlying principles, potential benefits, and associated trade-offs. This is a burgeoning field that seeks to balance computational efficiency with acceptable accuracy. The paper highlights opportunities where these techniques can be effectively applied, such as in applications where perfect accuracy is not a strict requirement. This paper presents assessments of applying approximate computing techniques in various applications, especially machine learning algorithms (ML) and IoT. Furthermore, this review underscores the challenges encountered in implementing approximate computing techniques and highlights potential future research avenues. The anticipation is that this survey will stimulate further discourse and underscore the necessity for continued research and development to fully exploit the potential of approximate computing.

In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore, the input stream is truncated with an erratum mending unit to roughly construct the partial products. For an aggregation of PPs, an approximate Wallace tree is taken into consideration to further minimize hardware expenses. Consequently, the suggested design’s latency, utilized area, and power usage are largely reduced. The Xilinx Vertex device is expedited, given the synthesis of the suggested multichannel realization with 16 taps, which is simulated using the Verilog formulary. It is observed that the filter structure with one channel produced the desired results, and the system’s frequency can support up to 429 MHz with a reduced area. Utilizing TSMC 180 nm CMOS technology and the Cadence RC compiler, cell-level performance is also achieved.

In this paper, two new approximate subtractors are presented. The proposed circuits are implemented based on gate diffusion input (GDI) and dynamic threshold (DT) techniques and are named Proposed-1 and Proposed-2. The Proposed-1 subtractor has 10 transistors, while Proposed-2 has 12 transistors. Subtractors are implemented by 32 nm carbon nanotube field effect transistor (CNTFET) technology. Various studies have been performed and show the high efficiency and performance of the circuits in different conditions without reducing their output voltage, which is caused by the use of DT in their implementation. The proposed circuits use XOR and NOT gates, both of which have 4 out of 8 error states. The presented subtractors can be implemented in an unsigned non-recovery divider with different structures including vertical, horizontal, square and triangular, etc., and finally, they can be used in image processing applications to detect the difference between two images, either medical or standard images. The simulation results show the better performance of the proposed circuits, Proposed-1 and Proposed-2 save PDP of 88.36% and 83.25%, respectively.

Distributed computing frameworks are the fundamental component of distributed computing systems. They provide an essential way to support the efficient processing of big data on clusters or cloud. The size of big data increases at a pace that is faster than the increase in the big data processing capacity of clusters. Thus, distributed computing frameworks based on the MapReduce computing model are not adequate to support big data analysis tasks which often require running complex analytical algorithms on extremely big data sets in terabytes. In performing such tasks, these frameworks face three challenges: computational inefficiency due to high I/O and communication costs, non-scalability to big data due to memory limit, and limited analytical algorithms because many serial algorithms cannot be implemented in the MapReduce programming model. New distributed computing frameworks need to be developed to conquer these challenges. In this paper, we review MapReduce-type distributed computing frameworks that are currently used in handling big data and discuss their problems when conducting big data analysis. In addition, we present a non-MapReduce distributed computing framework that has the potential to overcome big data analysis challenges.

Abstract Clustering a big dataset without knowing the number of clusters presents a big challenge to many existing clustering algorithms. In this paper, we propose a Random Sample Partition-based Centers Ensemble (RSPCE) algorithm to identify the number of clusters in a big dataset. In this algorithm, a set of disjoint random samples is selected from the big dataset, and the I-niceDP algorithm is used to identify the number of clusters and initial centers in each sample. Subsequently, a cluster ball model is proposed to merge two clusters in the random samples that are likely sampled from the same cluster in the big dataset. Finally, based on the ball model, the RSPCE ensemble method is used to ensemble the results of all samples into the final result as a set of initial cluster centers in the big dataset. Intensive experiments were conducted on both synthetic and real datasets to validate the feasibility and effectiveness of the proposed RSPCE algorithm. The experimental results show that the ensemble result from multiple random samples is a reliable approximation of the actual number of clusters, and the RSPCE algorithm is scalable to big data.

This paper presents the hardware design of fast and low-cost denoising filters suitable to be exploited in the enabling technologies for Industry 5.0. A novel approximate computing strategy is introduced to reduce the computational complexity of the image denoising operation and to comply with real-time requirements. Firstly, it is demonstrated that the novel approximate approach can be helpfully exploited in the design of reconfigurable denoising filters able to reach image qualities as close as possible to the precise software counterparts. The reconfigurability leads to hardware architectures run-time adaptable to different levels of noise, whereas the adopted approximation strategy limits hardware resources and energy requirements. Quality tests, performed at various image and kernel sizes, and noise standard deviations, demonstrate that the approximate denoising approach presented here reaches PSNR and SSIM comparable with the precise denoise filtering. In comparison with state-of-the-art FPGA-based competitors, the novel filters reduce the resources requirements by up to 70%, achieve frame rates up to 35 times higher, and dissipate more than 45% lower power. When implemented within the XC7Z7020 FPGA device, a $5\times 5$ filter designed as proposed here denoises $512\times 512$ grayscale images using only 1689 LUTs, 2635 Flip-Flops and 32 DSPs. Moreover, it processes up to 926.8 frames per second, consumes just 63mW @ 244MHz and, with a noise standard deviation equal to 10, it achieves an average PSNR of $\sim 33$ dB with an average SSIM of ~0.86.

Design methodologies for approximation of medium to large-scale accelerators have largely relied on search-based design space exploration. Due to the enormously sized solution space, Artificial Intelligence (AI) based heuristic search has remained one of the most common techniques to explore cost and performance trade-offs. As a sub-class of AI techniques, Monte Carlo Tree Search (MCTS) has recently shown great potential as an intelligent stochastic search algorithm to solve computational problems with large branching factors. MCTS employs reinforced learning that combines past statistics and stochastic processes to traverse new paths in the search tree. Inspired by the success of MCTS in the games domain (AlphaGo), it has been recently applied to explore the solution space of approximate circuits. In this paper, a modified MCTS-based intelligent search technique is proposed that can handle huge search space for approximation of fairly large benchmark circuits. The proposed learning-based heuristic for MCTS directs the search towards deeper nodes in the search tree resulting in a rather asymmetric tree to efficiently utilize the search budget on the exploration of more promising nodes in the design space. The modified MCTS algorithm is based on reinforced learning where an agent uses past information to improve the overall gain. Experimental results confirm that the proposed heuristics can reach out to deeper nodes in the search tree which account for larger area savings in the context of approximate computing. The modified search algorithm enables 34.23% more area savings than the original search algorithm.

Many graph-based algorithms in high performance computing (HPC) use approximate solutions due to having algorithms that are computationally expensive or serial in nature. Neural acceleration, i.e., the process of speeding up approximation computation elements via artificial neural networks, is relatively new and has not focused on HPC graph-based algorithms. In this paper, we propose a starting point for applying models for neural acceleration to graph-based HPC algorithms utilizing an understanding of the connectivity computational pattern, recursive neural networks, and graph neural networks. We demonstrate these techniques on the problem related to the utility functions of sparse matrix ordering and fill-in (i.e., zero elements becoming nonzero during factorization) calculations. The problem of sparse matrix ordering is commonly used for issues related to load balancing, improving memory reuse, or reducing computational and memory costs in direct sparse linear solver methods. These utility functions are ideal for demonstration as they comprise a number of different graph-based subproblems, and thus demonstrate the usefulness of our method over a wide range. We show that we can accurately approximate the best ordering and the nonzero count of the sparse factorization matrix while speeding up the calculation by as much as $30.3\times $ over the traditional serial method.

The importance of multi-valued data transmission for improving communication throughput has become apparent with the explosive growth o communication and computing demands. Although modulation schemes with denser constellations can provide increased data rates, they require a higher signal-to-noise ratio. On the other hand, sparser constellation formats offer reliable communication thanks to their greater tolerance to noise, but the throughput is inferior to that with denser constellations. Here, we introduce an approximate computing/communication that involves the critical notion of quality of information to tolerate the trade-off between throughput and reliability, which will be important in future high-performance optical communications and interconnects. In this study, we experimentally demonstrate a dynamically configured transmission scheme where different modulation formats are adopted according to the importance of bit sequences on the basis of Radio-over-Fiber (RoF) systems in transmitting floating-point numbers. The proposed system demonstrated an increased gross throughput of at least 25.1%, while errors in the transmitted floating-point numbers were uniformly bounded.

A ternary-weight neural network (TWN) inspired keyword spotting (KWS) processor is proposed to support complicated and variable application scenarios. To achieve high-precision recognition of ten keywords under 5 dB~Clean wide range of background noises, a convolution neural network consists of four convolution layers and four fully connected layers, with modified sparsity-controllable truncated Gaussian approximation-based ternary-weight training is used. End-to-end optimization composed of three techniques is utilized: 1) the stage-by-stage bit-width selection algorithm to optimize the hardware overhead of FFT; 2) the lossy compressed TWN with symmetric kernel training (SKT) and dedicated internal data reuse computation flow; and 3) the error intercompensation approximate addition tree to reduce the computation overhead with marginal accuracy loss. Fabricated in an industrial 22-nm CMOS process, the processor realizes up to ten keywords in real-time recognition under 11 background noise types, with the accuracy of 90.6%@clean and 85.4%@5 dB. It consumes an average power of $3.8 ~\mu \text{W}$ at 250 kHz and the normalized energy efficiency is $2.79\times $ higher than state of the art.

The capabilities of artificial neural networks are rapidly evolving, so are the expectations for them to solve ever more challenging tasks in numerous everyday situations. Larger, more complex networks and the need to execute them efficiently on edge devices are the two counteracting requirements of this trend. Novel devices and computation techniques show promising characteristics to address this challenge. A huge design space covering different combinations of neural networks and hardware architectures using these technologies needs to be explored. An efficient design flow is, therefore, crucial for a good quality of service. This work reviews a wide range of simulation tools for novel memristive devices and analyzes their applicability for the design space exploration. A modular toolflow is proposed that shrinks down the large design space step-by-step using state-of-the-art optimization techniques and builds upon existing tools to find the best trade-offs between network accuracy and hardware requirements.

This work aims to measure the impact of approximate computing on a case study of traffic dynamics metering on a System-on-Chip edge computing device. Firstly, the study proposes a baseline implementation of the metering system in C++. To analyze the application in detail, study profiled the baseline using a built-in instrumented profiler, presenting the overall performance of each of its parts. During the hotspot analysis, some parts had optimization opportunities exploitable by multi-threading and approximate computing techniques, particularly frame skipping, which is inspired by the loop perforation approximate technique. The first optimization employed was multi-threading, which led to a 1.32x speedup on the application without introducing errors in the metrics. Then, the meter was optimized by using frame skipping. This work demonstrated that adaptatively modifying the number of frames skipped improved the error in the final metrics compared to keeping it fixed. In terms of performance, the frame skipping brought the overall speed up to 1.76x. Approximate computing, in particular, frame skipping, managed to contribute up to 25% of the overall speedup, managing to accelerate the meter from 8.7 frames per second to 15 fps in the most critical case in exchange for some numerical error on the final metrics.

The calculation of square roots is a frequently used operation in control systems of power electronics for different applications: motor drives, power converters, etc. At the same time, the execution of this procedure significantly loads microcontrollers and uses its power, which can be utilized for performing other important tasks. Therefore, it restricts the size of code, which can be processed by the microcontroller and compels developers to limit the number of functions, or to decrease execution frequency of a program. Thus, the calculation of square roots is a bottle-neck in implementation of high-performance control systems, thus effective optimization of this task is extremely important in modern and efficient devices. In respect that many applications do not need precise calculation of square roots, the optimization of execution time can be achieved by decreasing of precision of the result. The proposed technique is based on the approximation of parabola with hyperbola, which allows you to rapidly find the approximate value of a square root. Taking into account that many digital signal processors (DSP) are not equipped with an effective divider, the developed algorithm does not use divisions, so it can be executed faster. The payback for this optimization is approximation error with a maximum of 0.5%, however, it is acceptable for the overwhelming majority of control systems.

This paper proposes a background noise adaptive energy-efficient keywords recognition processor with Reusable DNN (RDNN) and reconfigurable architecture. To reduce power consumption while maintaining the recognition accuracy of different background noises, the SNR prediction module determines whether the computing mode is low power consumption mode (LPM) or high performance mode (HPM). In LPM, DNN-shift (shift-based deep neural network) is used to achieve high recognition accuracy in a low background noise environment; in HPM, DNN-8bit (8bit weighted deep neural network) is used to achieve low power consumption in a high background noise environment. And the two modes share most of the hardware, and approximate computing is introduced to further reduce power consumption. Evaluated under 22nm process technology, this work can support up to 10 keywords recognition with the power consumption of $11.2~\mu \text{W}$ for high background noise and $7.3~\mu \text{W}$ for low background noise.

Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. Computing the error of the approximated design is an essential step to determine its quality. The computation time for determining the error can become very large, effectively rendering the entire logic approximation procedure infeasible. In this work we extensively analyze various error metrics and approximation operations. We present methods to accelerate the computation of error metric computations by 1) exploiting structural information of the function obtained by applying the analyzed operations and 2) computing estimates of the metrics for multi-output Boolean functions represented as Binary Decision Diagrams (BDDs). We further present a novel greedy, bucket-based BDD minimization framework employing the newly proposed error metric computations to produce Pareto-optimal solutions with respect to BDD size and multiple error metrics. The applicability of the proposed minimization framework is demonstrated by an experimental evaluation. We can report considerable speedups while, at the same time, creating high-quality approximated BDDs. The presented framework is publicly available as open-source software on GitHub.

The advent of the Internet of Things (IoT) has revolutionized the way we, as a society, perform different daily tasks, such as healthcare. The Internet of Health Things (IoHT) is an example of the IoT specialization handling sensitive user data and applications requiring solutions to address different security and privacy issues. IoHT requires security mechanisms in communication. However, these mechanisms need to consider the limitations of the IoHT devices and communication. Hence, symmetric cryptography is suitable to IoHT once it uses less computational and communication resources than asymmetric cryptography. But, symmetric cryptography relies on the agreement of the cryptography material (e.g., the cryptography key) among the devices, a challenge in networks with resource constraints, such as IoHT. Therefore, this article presents a Low memORy symmEtric-key geNerAtion (LORENA) method based on group secret key agreement protocol for IoHT environments. Evaluations have focused on computational efficiency, data security requirements, and scalability in a network with up to ten devices per group using a simulator and a device with limited computational resources. Results show that the protocol is lightweight, secure, and feasible to IoHT networks, presenting a linear growth in the 128-bit key distribution time for each device entering the group.

In modern power constrained applications, as with most of those belonging to the Internet-of-Things world, custom hardware supports are ever more commonly adopted to deploy artificial intelligence algorithms. In these operating environments, limiting the power dissipation as much as possible is mandatory, even at the expense of reduced computational accuracy. In this paper we propose a novel prediction method to identify potential predominant features in convolutional layers followed by down-sampling layers, thus reducing the overall number of convolution calculations. This approximation down-sampling strategy has been exploited to design a custom hardware architecture for the inference of Convolutional Neural Network (CNN) models. The proposed approach has been applied to several benchmark CNN models and we achieved an overall energy saving of up to 70% with an accuracy loss lower than 3%, with respect to baseline designs. Performed experiments demonstrate that, when adopted to infer the Visual Geometry Group-16 (VGG16) network model, the proposed architecture implemented on a Xilinx Z-7045 chip and on the STM 28nm process technology dissipates only 680 and 21.9 mJ/frame, respectively. In both cases, the novel design overcomes several state-of-the-art competitors in terms of energy-accuracy drop product.

Convolutional Neural Networks (CNNs) exhibit significant performance enhancements in several machine learning tasks such as surveillance, intelligent transportation, smart grids and healthcare systems. With the proliferation of physical things being connected to internet and enabled with sensory capabilities to form an Internet of Thing (IoT) network, it is increasingly important to run CNN inference, a computationally intensive application, on the resource constrained IoT devices. Object detection is a fundamental computer vision problem that provides information for image understanding in several artificial intelligence (AI) applications in smart cities. Among various object detection algorithms, CNN has emerged as a new paradigm to improve the overall performance. The Multiply-accumulate (MAC) operations, which are used repeatedly in the convolution layers of CNN, hold extreme computational complexity. Hence, the overall computational workloads and their respective energy consumption of any CNN applications are on the rise. To overcome these escalating challenges, approximate computing mechanism has played a vital role in reducing power and area of computation intensive CNN applications. In this paper, we have designed an approximate MAC architecture, termed Shift and Accumulator Unit (SAC), for the error-resilient CNN based object detection algorithm targeting embedded platforms. The proposed computing unit deliberately trades accuracy to reduce design complexity and power consumption, thus suiting the resource constrained IoT devices. The pipeline architecture of the SAC unit saves approximately 1.8× clock cycles than the non-pipeline SAC architecture. The performance evaluation shows that the proposed computing unit has better energy efficiency and resource utilization than the accurate multiplier and state-of-the-art approximate multipliers without noticeable deterioration in overall performance.

Deep Neural Networks (DNNs) are computationally and memory intensive, which present a big challenge for hardware, especially for resource-constrained devices such as Internet-of-Things (IoT) nodes. This paper introduces a new method to improve DNNs performance by fusing approximate computing with data reuse techniques for image recognition applications. First, starting from the pre-trained network, then the DNNs weights are approximated based on the linear and quadratic approximation methods during the retraining phase to reduce the DNN model size and number of arithmetic operations. Then, the DNNs weights are replaced with the linear/quadratic coefficients to execute the inference so that different DNNs weights can be computed using the same coefficients. That leads to a repetition of the weights, which enables the reuse of the DNN sub-computations (computational reuse) and leverages the same data (data reuse) to reduce DNNs computations memory accesses, and improve energy efficiency, albeit at the cost of increased training time. Complete analysis for MNIST, Fashion MNIST, CIFAR 10, CIFAR 100, and tiny ImageNet datasets is presented for image recognition, where different DNN models are used, including LeNet, ResNet, AlexNet, and VGG16. Our results show that the linear approximation achieves $1211.3\times $ , $21.8\times $ , $700\times $ , and $19.3\times $ on LeNet-5 MNIST, LeNet Fashion MNIST, VGG16 and ResNet-20. respectively, with small accuracy loss. Compared to the state-of-the-art Row Stationary (RS) method, the proposed architecture saved 54% of the total number of adders and multipliers needed. Overall, the proposed approach is suitable for IoT edge devices as it reduces computing complexity, memory size, and memory access with a small impact on accuracy.

A convolutional neural network (CNN) classifies images with high accuracy. However, CNN operation requires a large number of computations which consume a significant amount of power when implemented on hardware. Precision scaling has been recently used to reduce the hardware requirements and power consumption. In this paper, we present an energy-efficient precision-scaled CNN (EEPS-CNN) architecture. Furthermore, the Field Programmable Gate Array (FPGA) is reconfigured during run time using Dynamic Partial Reconfiguration (DPR). If the battery level decreases, the EEPS-CNN design with the most appropriate power consumption is configured on the FPGA. DPR enables recognition applications to run at a low power budget while sacrificing minor accuracy instead of termination. The proposed architecture is implemented on Xilinx XC7Z020 FPGA and is evaluated on three datasets: MNIST, F-MNIST, and SVHN datasets. The results show a 2.2X, 2.39X, and 2.38X reduction in the energy consumption, respectively, while using only 7 bits to represent all inputs and network parameters. The accuracy of the proposed EEPS-CNN is only 0.53%, 3.67%, and 0.88% less than 32-bit floating-point architectures for MNIST, F-MNIST, and SVHN, respectively. Moreover, the results show up to 92.91X and 4.84X reductions in the power and energy consumption of the proposed EEPS-CNN compared to related designs developed for the MNIST dataset.

With advancements in machine learning technology, networks are becoming increasingly complex, and the extent of the computation involved is increasing. Consequently, the computation time and power consumption of the learning process are increased. The error tolerance of neural networks has attracted attention as an approach to solving this problem. Because neural networks can tolerate small errors, it is possible to reduce the calculation speed and power consumption at the expense of accuracy. In this study, we propose a method to reduce the power consumption of the circuit by lowering the operating voltage of the static random-access memory (SRAM) that is utilized to store the weights. In the proposed method, using two different operating voltages of SRAM, we used different bit error rates (BERs) for error-tolerant and non-error-tolerant. We demonstrated the relationship between the BER and recognition rate, and the appropriate combination of the BER and circuit configuration that maintains a high recognition rate.

Error mitigation techniques, such as Triple Modular Redundancy, introduce very large overheads. To alleviate this overhead, approximate techniques can be used. In this work we propose a novel approximate error mitigation technique based on using redundant circuits with lower resolution. As a representative case study, the approach is demonstrated for a Fast Fourier Transform, for which an optimized architecture is proposed. The approach is validated through fault injection. Experimental results show that Reduced Resolution Redundancy can significantly reduce the overhead and achieve an excellent error mitigation performance and a low sensitivity to uncorrectable errors.

Multipliers are among the most critical arithmetic functional units in many applications, and those applications commonly require many multiplications which result in significant power consumption. For applications that have error tolerance, employing an approximate multiplier is an emerging method to reduce critical path delay and power consumption. An approximate multiplier can trade off accuracy for lower energy and higher performance. In this paper, we not only propose an approximate 4-2 compressor with high accuracy, but also an adjustable approximate multiplier that can dynamically truncate partial products to achieve variable accuracy requirements. In addition, we also propose a simple error compensation circuit to reduce error distance. The proposed approximate multiplier can adjust the accuracy and power required for multiplications at run-time based on the users’ requirement. Experimental results show that the delay and the average power consumption of the proposed adjustable approximate multiplier can be reduced by 27% and 40.33% (up to 72%) when compared to the Wallace tree multiplier. Moreover, we demonstrate the suitability and reconfigurability of our proposed multiplier in convolutional neural networks (CNNs) to meet different requirements at each layer.

Approximate adders are some of the fundamental arithmetic operators that are being employed in error-resilient applications, to achieve performance/energy/area gains. This improvement usually comes at the cost of some accuracy and, therefore, requires prior error analysis, to select an approximate adder variant that provides acceptable accuracy. Most of the state-of-the-art error analysis techniques for approximate adders assume input bits and operands to be independent of one another, while some also assume the operands to be uniformly distributed. In this paper, we analyze the impact of these assumptions on the accuracy of error estimation techniques, and we highlight the need to address these assumptions, to achieve better and more realistic quality estimates. Based on our analysis, we propose DAEM, a data- and application-aware error analysis methodology for approximate adders. Unlike existing error analysis models, we neither assume the adder operands to be uniformly distributed nor assume them to be independent. Specifically, we use 2D joint input probability mass functions (PMFs), populated using sample data, in order to incorporate the data and application knowledge in the analysis. These 2D joint input PMFs, along with 2D error maps of approximate adders, are used to estimate the error PMF of an adder network. The error PMF is then utilized to compute different error measures, such as the mean squared error (MSE) and mean error distance (MED). We evaluate the proposed error analysis methodology on audio and video processing applications, and we demonstrate that our methodology provides error estimates having a better correlation with the simulation results, as compared to the state-of-the-art techniques.

In the era of smart Internet-of-Things, convolutional neural network (CNN) models with low computational overhead are crucial for low-latency applications in resource-constrained embedded devices. The performance and efficiency of multiplication operations play a vital role in accelerating and optimizing CNN computation. In this article, we propose the MA4C technique, which reduces CNN computation overhead by converting a pretrained CNN’s parameters into approximated minimum signed digit (MSD) representations. MSD representation contains fewer non-zero digits on average compared to the binary representation of a number. The proposed scheme approximates the MSD representations by only considering a specified number of most significant digits. The MA4C technique reduces the computational complexity of multipliers by reducing the number of partial sums. The proposed MSD approximation was applied on various DNN models, and their performance was analyzed for different datasets, varying CNN depth, and network configuration. Implementation of our proposed method on FPGA reduced the logic circuits and multiplier latency by up to 4.2× and 1.2× respectively compared to an 8-bit Booth multiplier for most CNN models.

We present taffo, a framework that automatically performs precision tuning to exploit the performance/accuracy trade-off. In order to avoid expensive dynamic analyses, taffo leverages programmer annotations which encapsulate domain knowledge about the conditions under which the software being optimized will run. As a result, taffo is easy to use and provides state-of-the-art optimization efficacy in a variety of hardware configurations and application domains. We provide guidelines for the effective exploitation of taffo by showing a typical example of usage on a simple application, achieving a speedup up to 60% at the price of an absolute error of 3.53×10−5. taffo is modular and based on the solid llvm technology, which allows extensibility to improved analysis techniques, and comprehensive support for the most common precision-reduced data types and programming languages. As a result, the taffo technology has been selected as the precision tuning tool of the European Training Network on Approximate Computing.

Performing inference of complex machine learning (ML) algorithms at the edge is becoming important to unlink the system functionality from the cloud. However, the ML models increase complexity faster than the available hardware resources. This research aims to accelerate machine learning by offloading the computation to low-end FPGAs and using approximate computing techniques to optimise resource usage, taking advantage of the inaccurate nature of machine learning models. In this paper, we propose a generic matrix multiply-add processing element design, parameterised in datatype, matrix size, and data width. We evaluate the resource consumption and error behaviour while varying the matrix size and the data width given a fixed-point data type. We determine that the error scales with the matrix size, but it can be compensated by increasing the data width, posing a trade-off between data width and matrix size with respect to the error.

This paper presents a low‐cost two‐stage approximate multiplier for bfloat16 (brain floating‐point) data processing. For cost‐efficient approximate multiplication, the first stage implements Mitchell's algorithm that performs the approximate multiplication using only two adders. The second stage adopts the exact multiplication to compensate for the error from the first stage by multiplying error terms and adding its truncated result to the final output. In our design, the low‐cost multiplications in both stages can reduce hardware costs significantly and provide low relative errors by compensating for the error from the first stage. We apply our approximate multiplier to the convolutional neural network (CNN) inferences, which shows small accuracy drops with well‐known pre‐trained models for the ImageNet database. Therefore, our design allows low‐cost CNN inference systems with high test accuracy.

Spiking Neural Networks (SNNs) have shown capabilities of achieving high accuracy under unsupervised settings and low operational power/energy due to their bio-plausible computations. Previous studies identified that DRAM-based off-chip memory accesses dominate the energy consumption of SNN processing. However, state-of-the-art works do not optimize the DRAM energy-per-access, thereby hindering the SNN-based systems from achieving further energy efficiency gains. To substantially reduce the DRAM energy-per-access, an effective solution is to decrease the DRAM supply voltage, but it may lead to errors in DRAM cells (i.e., so-called approximate DRAM). Toward this, we propose EnforceSNN, a novel design framework that provides a solution for resilient and energy-efficient SNN inference using reduced-voltage DRAM for embedded systems. The key mechanisms of our EnforceSNN are: (1) employing quantized weights to reduce the DRAM access energy; (2) devising an efficient DRAM mapping policy to minimize the DRAM energy-per-access; (3) analyzing the SNN error tolerance to understand its accuracy profile considering different bit error rate (BER) values; (4) leveraging the information for developing an efficient fault-aware training (FAT) that considers different BER values and bit error locations in DRAM to improve the SNN error tolerance; and (5) developing an algorithm to select the SNN model that offers good trade-offs among accuracy, memory, and energy consumption. The experimental results show that our EnforceSNN maintains the accuracy (i.e., no accuracy loss for BER ≤ 10−3) as compared to the baseline SNN with accurate DRAM while achieving up to 84.9% of DRAM energy saving and up to 4.1x speed-up of DRAM data throughput across different network sizes.

As one of the most promising energy-efficient emerging paradigms for designing digital systems, approximate computing has attracted a significant attention in recent years. Applications utilizing approximate computing (AxC) can tolerate some loss of quality in the computed results for attaining high performance. Approximate arithmetic circuits have been extensively studied; however, their application at system level has not been extensively pursued. Furthermore, when approximate arithmetic circuits are applied at system level, error-accumulation effects and a convergence problem may occur in computation. Multiple approximate components can interact in a typical datapath, hence benefiting from each other. Many applications require more complex datapaths than a single multiplication. In this paper, a hardware/software co-design methodology for adaptive approximate computing is proposed. It makes use of feature constraints to guide the approximate computation at various accuracy levels in each iteration of the learning process in Artificial Neural Networks (ANNs). The proposed adaptive methodology also considers the input operand distribution and the hybrid approximation. Compared with a baseline design, the proposed method significantly reduces the power-delay product while incurring in only a small loss of accuracy. Simulation and a case study of image segmentation validate the effectiveness of the proposed methodology.

This paper proposes a low-cost approximate dynamic ranged multiplier and describes its use during the training process on convolutional neural networks (CNNs). It has been noted that the approximate multiplier can be used in the convolution of CNN’s forward path. However, in CNN inference on a post-training quantization with a pre-trained model, erroneous convolution output from highly approximate multipliers significantly degrades performance. On the other hand, with the CNN model based on an approximate multiplier, the approximation-aware training process can optimize its learnable parameters, producing better classification results considering the approximate hardware. We analyze the error distribution of the approximate dynamic ranged multiplication and characterize it in order to find the most suitable approximate multiplier design. Considering the effects of normalizing the biased convolution outputs, a low standard deviation of relative errors with respect to the multiplication outputs leads to a negligible accuracy drop. Based on these facts, the hardware costs of the proposed multiplier can be further reduced by adopting the partial products’ inaccurate compression, truncated input fraction, and reduced-width multiplication output. When the proposed approximate multiplier is applied to the residual convolutional neural networks for the CIFAR-100 and Tiny-ImageNet datasets, the accuracy drops of the approximation-aware training results are negligible compared with those using 32-bit floating-point CNNs.

Spiking neural networks (SNNs) represent a promising alternative to conventional neural networks. In particular, the so-called Spike-by-Spike (SbS) neural networks provide exceptional noise robustness and reduced complexity. However, deep SbS networks require a memory footprint and a computational cost unsuitable for embedded applications. To address this problem, this work exploits the intrinsic error resilience of neural networks to improve performance and to reduce hardware complexity. More precisely, we design a vector dot-product hardware unit based on approximate computing with configurable quality using hybrid custom floating-point and logarithmic number representation. This approach reduces computational latency, memory footprint, and power dissipation while preserving inference accuracy. To demonstrate our approach, we address a design exploration flow using high-level synthesis and a Xilinx SoC-FPGA. The proposed design reduces $20.5\times $ computational latency and $8\times $ weight memory footprint, with less than 0.5% of accuracy degradation on a handwritten digit recognition task.

Mez is a novel publish-subscribe messaging system for latency sensitive multi-camera machine vision applications at the IoT Edge. The unlicensed wireless communication in IoT Edge systems are characterized by large latency variations due to intermittent channel interference. To achieve user specified latency in the presence of wireless channel interference, Mez takes advantage of the ability of machine vision applications to temporarily tolerate lower quality video frames if overall application accuracy is not too adversely affected. Control knobs that involve lossy image transformation techniques that modify the frame size, and thereby the video frame transfer latency, are identified. Mez implements a network latency feedback controller that adapts to channel conditions by dynamically adjusting the video frame quality using the image transformation control knobs, so as to simultaneously satisfy latency and application accuracy requirements. Additionally, Mez uses an application domain specific design of the storage layer to provide low latency operations. Experimental evaluation on an IoT Edge testbed with a pedestrian detection machine vision application indicates that Mez is able to tolerate latency variations of up to 10x with a worst-case reduction of 4.2% of the application accuracy F1 score metric. The performance of Mez is also experimentally evaluated against state-of-the-art low latency NATS messaging system.

Approximate computing has emerged as an efficient solution for energy saving at the expense of calculation accuracy, especially for floating-point operation intensive applications, which have urgent demands for some uniform design frameworks for floating-point approximate computing combining the approximate computing techniques with the metrics of applications. In this paper, a simple approximate method with a zero-mean noise for the mantissa was introduced firstly, called PAM. Secondly, based on the proposed approximate method, the corresponding noise propagation models for floating-point operations were built, including floating-point addition, subtraction, and multiplication. Thirdly, a uniform design framework, which is only related to the operational-level topology of applications, was presented. The presented design framework can be used to evaluate the quality of data produced by applications before the circuit design is completed, and the efficient bit width of the mantissa can be obtained under specific requirements, which is also suitable for truncation. Finally, we studied the feasibility of the proposed design framework through two typical applications of image processing, edge detection and Gaussian filtering. The experimental results of edge detection have shown that our proposed design framework could effectively predict efficient bit width under the specific peak signal-to-noise ratio, with a difference of 1–2 bits in extreme situations. The Gaussian filtering experiment has demonstrated that the proposed design framework could apply to applications with complex calculations and structures.

In this paper, we propose a methodology for designing low error efficient approximate adders for FPGAs. The proposed methodology utilizes FPGA resources efficiently to reduce the error of approximate adders. We propose two approximate adders for FPGAs using our methodology: low error and area efficient approximate adder (LEADx), and area and power efficient approximate adder (APEx). Both approximate adders are composed of an accurate and an approximate part. The approximate parts of these adders are designed in a systematic way to minimize the mean square error (MSE). LEADx has lower MSE than the approximate adders in the literature. The 32-bit LEADx with 16-bit approximation has 20% lower MSE than the approximate adder with the lowest MSE in the literature. The 16-bit APEx with 8-bit approximation has the same area, 60% lower MSE, and 4.5% less power consumption in Xilinx Virtex 7 FPGA than the smallest and lowest power consuming approximate adder in the literature. APEx has smaller area and lower power consumption than the other approximate adders in the literature. As a case study, the approximate adders are used in video encoding application. LEADx provided better quality than the other approximate adders for video encoding application. Therefore, our proposed approximate adders can be used for efficient FPGA implementations of error tolerant applications.