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This paper presents an efficient wavelet based numerical method for analyzing functional and dynamic crosstalk of CMOS driven coupled copper (Cu) interconnects known as Multi-Resolution Time Domain (MRTD),wherein, the CMOS drivers are modeled using nth-power law model. The performance of the proposed MRTD method is evaluated through recursive simulations in HSPICE environment and compared with the conventional Finite Difference Time Domain (FDTD) method at 32-nm technology node for global interconnects of length 1mm, where the computations of the proposed model and conventional FDTD are carried out using MATLAB. For different number of test cases, the proposed MRTD method gives an average error of 0.14 % and 1.9 % for peak crosstalk noise and peak noise timing, respectively, with respect to HSPICE results. Also, the dynamic crosstalk noise on victim line of the proposed MRTD method are in close agreement with those of HSPICE. The results show the dominance of the proposed MRTD method over the conventional FDT method regarding accuracy. The proposed MRTD method is also extended for three-mutuallycoupled interconnect lines for crosstalk analysis, with an average error less than 1 % when compared to that of more than 3 % using the conventional FDTD method. Moreover, for the transient analysis, the MRTD method is more time efficient than HSPICE.

This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%–50% and a falling-delay improvement of 25%–47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%–43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire.