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This article discusses the issue of studying the parameters of the bounce of electrical contacts of switches in digital systems. Digital circuits of bounce analyzer are described. The results of experimental studies of the behavior of electrical contacts of various buttons and switches are presented. It is shown that various electric switches have random and unique characteristics, which can be used to solve the problems of random numbers generating, identifying of digital devices and user’s authentication. Prototyping of the proposed circuits was carried out on Digilent ZYBO Z7-10 debug boards, digital circuits were designed in VHDL for the Xilinx Zynq-7000 FPGA chip.

Computational cost in metaheuristics such as Evolutionary Algorithm (EAs) is often a major concern, particularly with their ability to scale. In data-based training, traditional EAs typically use a significant portion, if not all, of the dataset for model training and fitness evaluation in each generation. This makes EA suffer from high computational costs incurred during the fitness evaluation of the population, particularly when working with large datasets. To mitigate this issue, we propose a Machine Learning (ML)-driven Distance-based Selection (DBS) algorithm that reduces the fitness evaluation time by optimizing test cases. We test our algorithm by applying it to 24 benchmark problems from Symbolic Regression (SR) and digital circuit domains and then using Grammatical Evolution (GE) to train models using the reduced dataset. We use GE to test DBS on SR and produce a system flexible enough to test it on digital circuit problems further. The quality of the solutions is tested and compared against state-of-the-art and conventional training methods to measure the coverage of training data selected using DBS, i.e., how well the subset matches the statistical properties of the entire dataset. Moreover, the effect of optimized training data on run time and the effective size of the evolved solutions is analyzed. Experimental and statistical evaluations of the results show our method empowered GE to yield superior or comparable solutions to the baseline (using the full datasets) with smaller sizes and demonstrates computational efficiency in terms of speed.

This paper reports a new fractional-order Chua’s system with arctan function and an algorithm for determining the initial value of fractional-order hidden attractors. Firstly, dynamics of the system is investigated by employing the stability analysis, dissipativeness, phase diagrams, 0-1 test, bifurcation diagram and SampEn complexity measure. It shows rich dynamics in the proposed system. Secondly, using the proposed algorithm, the initial values of the new fractional-order Chua’s system are calculated. And according to two sets of initial conditions, hidden attractors are found and verified by the numerical simulation. Meanwhile, the basin attraction is analyzed to confirm that the hidden attractor is indeed not near the fixed point. Thirdly, the new fractional-order Chua’s system is implemented on the DSP platform, and the arctan function’s processing algorithm is proposed. The DSP experimental results show that the system can produce a pair of coexisting fractional-order hidden attractors, and the experimental results are consistent with the numerical simulation results. It verifies the effectiveness of the presented methods and shows the potential engineering application value of the proposed Chua’s system.

In this study, we propose a lightweight and low-latency advanced encryption standard (AES) accelerator. Instead of being connected to the bus through its own slave wrapper, the proposed AES accelerator is located within the slave wrapper of the static random-access memory (SRAM) and is directly attached to the SRAM. Hence, the AES accelerator can directly access data in the SRAM and share SRAM space for storing expanded keys, resulting in no time for transferring input and output data, no resource usage for storing keys, and no power wastage for repeated key expansion. The proposed AES accelerator has a latency of 53 clock cycles per encryption/decryption process and has a gate count of 2912 when synthesized using 28 nm process technology. The latency is similar to that of another AES accelerator with the same 32-bit data path; however, the size of the proposed accelerator is 46.0% smaller. Furthermore, compared with other AES accelerators with 8-bit data path, the proposed AES accelerator has a 3.0–22.0 times smaller latency with a slightly larger area.

A hydrogen maser is a high-precision time measurement instrument with high frequency stability and low frequency drift, which is widely used in satellite navigation, ground time keeping, frequency measurement, and other fields. An active hydrogen maser (AHM) is better than the current space passive hydrogen maser (PHM) in orbit in terms of its frequency stability and drift rate, but it has the disadvantages of large volume and weight. To further reduce the volume and weight of the circuit, this paper demonstrates a digital circuit control system based on a field-programmable gate array (FPGA). It uses digital temperature control, digital detectors, digital down-conversion, digital phase-locked loops, and other digital methods for temperature control, cavity auto-tuning, and crystal phase locking, which improve the integration and flexibility of the circuit system. Meanwhile, a tuning method based on hydrogen flow is proposed, which effectively solves the problem of fluctuations in hydrogen maser resonance frequency with changes in the external environment. Our experimental results show that the designed digital circuit control system meets the requirements of an oven-controlled crystal oscillator (OCXO) loop and a cavity loop. Its frequency stability can reach 2.6×10−13/1 s and 1.4×10−15/10,000 s, which is close to the stability index of ground active hydrogen maser. This scheme has certain practical engineering value, and can be used in the design of hydrogen masers for next-generation space navigation satellites, deep space exploration, and space stations.

Circuit designers are always faced with new obstacles as a result of the persistent trend in today's nanoscale technology to follow Moore's law. The complexities inherent in the production process have increased dramatically due to the rapid downscaling of integration. Parallel to this, the complexity and unpredictability of silicon chip flaws have increased, making circuit testing and diagnosis more challenging. The amount of test data has multiplied, and the criteria governing integrated circuit testing have grown both in size and in the complexity of correlation. The modern situation provides a useful framework for investigating novel machine learning-based test solutions. In this paper, the authors examine different recent developments in this developing field in the context of digital logic testing and diagnosis.

Thin-walled cylindrical shells are widely used in industries, such as the main parts of aircrafts, rockets, and submarines. Except for meeting the load-bearing capacities, such structures must also have good vibration and acoustic performances. However, it is still a challenge to control the multi-modal vibration of cylindrical shells at low frequencies. This study explores the cutting-edge local resonant piezoelectric metamaterials to control the low-frequency vibration of cylindrical shells. A novel cylindrical meta-shell with piezoelectric materials and digital circuits was proposed, and a multi-resonance transfer function is implemented in each digital circuit. A method to optimizing the parameters in the transfer function for the purpose of vibration reduction is developed. The vibrational characteristics of the meta-shell are numerically analyzed using the finite element method. Numerical results clearly demonstrate that by delicately designing the parameters in the transfer function, the meta-shell can reduce the peak amplitudes of the first five modes by 30 dB or more. Therefore, the proposed piezoelectric cylindrical meta-shell may open new opportunities in vibration mitigation of transport vehicles and underwater equipment.

Background. Cancer care involves a multidisciplinary approach to diagnosis and treatment of patients. A complex interaction of actors in the deployment of oncology services dictates usage of modern management technologies for improving the quality and efficiency of patient care through processes optimisation.Objectives. Provision of recommendations for patient routing based on research into the oncology service inter-level information exchange, integration of the process approach and electronic services. The lack of a unified information space with a regional oncology service has been explained. Measures are proposed for the patient routing optimisation as part of establishing a unified digital oncology service circuit.Methods. The oncology service was effectively remodelled through functional and information engineering of electronic services and the process management integration to establish a horizontal decision flow between facilities and employees on a process level bypassing the supervisor coordination. Statistical approaches were used to analyse the oncological patient population.Results. The following electronic services have been implemented: specialised patient referral routing, telemedicine and teleradiology. A comprehensive information framework has been created comprising medical, laboratory and radiological information subsystems integrated through regional electronic services of the unified state healthcare information platform. The goals, objectives, general principles, architecture and expected social economic impact on healthcare of Krasnodar Krai have been defined.Conclusion. Use of electronic services ensures an improved quality of specialised care and effective routing of patients. We perceive prospects of the integrated information platform in the extension and improvement of its subsystems’ functionality and content, sourcing more data providers and the circuit expansion to the federal and regional levels.

The paper contains an analysis of perspective structures of software and hardware equipment of universal digital design laboratories with the purpose of enabling laboratory classes of digital circuit design to be taken remotely. Implementation characteristics and usage experience of some of those structures applied to labs on several hardware related courses of « Computer science and computer engineering» program in NRNU MEPhI are presented. The paper also considers different aspects of usage of remote access enabled laboratory which should be taken into account to substantiate laboratory configuration from technical and economical standpoints. To increase equipment usage efficiency an approach to group several distinct projects to place them on a single FPGA chip is proposed. The paper shows advisability and gives an example of parametrizable virtual stand for remote debugging of FPGA projects.

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and image processing.

In the present research, we explore the possibility of utilizing a hardware-based neuromorphic approach to develop a tactile sensory system at the level of first-order afferents, which are slowly adapting type 1 (SA-I) and fast adapting type 1 (FA-I) afferents. Four spiking models are used to mimic neural signals of both SA-I and FA-I primary afferents. Next, a digital circuit is designed for each spiking model for both afferents to be implemented on the field-programmable gate array (FPGA). The four different digital circuits are then compared from source utilization point of view to find the minimum cost circuit for creating a population of digital afferents. In this way, the firing responses of both SA-I and FA-I afferents are physically measured in hardware. Finally, a population of 243 afferents consisting of 90 SA-I and 153 FA-I digital neuromorphic circuits are implemented on the FPGA. The FPGA also receives nine inputs from the force sensors through an interfacing board. Therefore, the data of multiple inputs are processed by the spiking network of tactile afferents, simultaneously. Benefiting from parallel processing capabilities of FPGA, the proposed architecture offers a low-cost neuromorphic structure for tactile information processing. Applying machine learning algorithms on the artificial spiking patterns collected from FPGA, we successfully classified three different objects based on the firing rate paradigm. Consequently, the proposed neuromorphic system provides the opportunity for development of new tactile processing component for robotic and prosthetic applications.

Nonlinear errors of sensor output signals are common in the field of inertial measurement and can be compensated with statistical models or machine learning models. Machine learning solutions with large computational complexity are generally offline or implemented on additional hardware platforms, which are difficult to meet the high integration requirements of microelectromechanical system inertial sensors. This paper explored the feasibility of an online compensation scheme based on neural networks. In the designed solution, a simplified small-scale network is used for modeling, and the peak-to-peak value and standard deviation of the error after compensation are reduced to 17.00% and 16.95%, respectively. Additionally, a compensation circuit is designed based on the simplified modeling scheme. The results show that the circuit compensation effect is consistent with the results of the algorithm experiment. Under SMIC 180 nm complementary metal-oxide semiconductor (CMOS) technology, the circuit has a maximum operating frequency of 96 MHz and an area of 0.19 mm2. When the sampling signal frequency is 800 kHz, the power consumption is only 1.12 mW. This circuit can be used as a component of the measurement and control system on chip (SoC), which meets real-time application scenarios with low power consumption requirements.