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Advanced front-end readout chips for medium and high energy nuclear physics experiments have shown an increasing trend towards digitization in recent years, increasing system integration and reducing power consumption. Guided by critical scientific goals, the Institute of Modern Physics of the Chinese Academy of Sciences is building a central scientific installation termed as the high intensity heavy-ion accelerator facility (HIAF). HIAF fragment separator (HFRS) is an important experimental device for radioactive beam physics research on the HIAF. The characteristics of HFRS strong current and the readout demand of the large area detectors put forward the requirements of high-count rate, high integration, and high time resolution for the front-end readout electronics, and therefore the development of the advanced digital front-end readout chip is urgently needed. The paper developed a high-count rate multi-channel time measurement and serial readout circuit (HMTRC) based on 180 nm complementary metal oxide semiconductor (CMOS) process, which can accelerate the development and iteration of such digital front-end readout chips. The HMTRC has now been integrated into a self-developed 16 channel digital-analogue hybrid front-end readout chip, EDIMS, for position sensitive detectors on HFRS. When a charge signal is input, the charge-sensitive amplifier (CSA) integrates the signal into an exponentially decaying voltage signal and fans out to the time path and the energy path. In the time path, the fast shaper inputs the output signal of the CSA into the discriminator after shaping, and outputs the self-triggering signal after comparing with the threshold. The digital first input first output (FIFO) memory in each channel records information such as the timestamp and channel number corresponding to the front time of the trigger signal. In the energy path, the slow shaper integrates the output signal of the CSA into a quasi-Gaussian signal. The output signal of the peak detect and hold circuit (PDH) follows the leading edge of the output signal of the slow shaper to detect and maintain peak energy information. The analog memory based on switched-capacitor arrays stores the information. The polling readout module based on the token ring logic reads out the stored charge and time information periodically and synchronously, which has advantages in the de-sparsification and de-randomization of nuclear events and the improvement of peak count rate. The chip has been fabricated and the HMTRC has a size of 535 μm×930 μm and a power consumption of 32.31 mW. The laboratory test system consists of a chip test board, a XILINX Kintex-7 development board, a host computer, a signal generator and an oscilloscope. The field programmable gate array (FPGA) on the development board provides the master clock and control signals for the chip under test. The output data from the chip are transferred to the development board by a high-speed connector, packaged by cache processing and uploaded to the host computer via the integrated logic analyzer for analysis. The test results show that the function of the HMTRC and the coarse time of the timestamps are in line with expectations, but the fine time of timestamp between each channel is different, and there is some error compared with the theoretical value. The test results also show that the accuracy of time resolution is better than 2 ns, which is as expected, and basically meets the requirements of the application. The next version of the design will optimize the inconsistency between the channels and fine time error of the timestamp, and add the inter-integrated circuit (I2C) or the serial peripheral interface (SPI) slow control module to improve the versatility of this circuit.