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The space environment is a very harsh operating environment, and space radiation can directly affect the operation of electronic devices causing total ionizing dose (TID), single event effect (SEE) and displacement damage (DD). For most devices TID and SEE are the two most dominant effects, the study of TID and SEE mechanism is one of the main tasks in modern spacecraft design. Previous studies show that there is a synergistic effect between TID and SEE. The TID will significantly affect the sensitivity of the SEE, and the effect rules and mechanisms are not consistent due to the different device process sizes and processes. There are few reports about the synergistic effect of SOI SRAM devices in the world, and the research on SOI SRAM with special memory cell structure has not been carried out. To further elucidate the synergistic effect between TID and SEE in SOI SRAM, an experimental study was conducted using a domestic 130 nm 7T SOI SRAM. The TID and SEE experiments were carried out at the China Institute of Atomic Energy TID test platform and HI-13 tandem accelerator SEE test platform. Before the SEE experiment, three groups of SOI SRAMs were irradiated by total dose of 300, 500 and 750 krad, respectively, and finally the change of the single event upset (SEU) cross section of the SOI SRAM after different doses TID irradiation was obtained. The experimental result shows that the SEU cross section of the SOI SRAM decreases to 80.5%, 66% and 50.5% at three LET values of 13.85, 21.8, and 37.4 MeV·cm2/mg after TID irradiation. There is no obvious difference found in the SEU cross section under different writing modes, which means that the synergistic effect of these devices has no data-dependent. The saturation cross section of the device also shows a trend of decreasing with increasing dose, up to 19.5%, and no significant change in the SEU threshold was found in this study. By analyzing the SEU cross section of flip-flop type 1→0 flip-flop and 0→1 flip-flop, it is found that the delay efficiency of the delay transistor N5 is the main reason for the influence on the SEU cross section. After the mechanism analysis, it is concluded that the delay transistor N5 has an increased equivalent off-state resistance due to the decrease of carrier mobility caused by TID, and this phenomenon is the main reason for the decrease of SEU cross section. The anti-SEE performance of SOI SRAM with special mechanism will be enhanced gradually with longer in-orbit time, which provides new insight for future electronic devices radiation-hardend.

The traditional Von Neumann architecture creates bottlenecks due to data movement. The compute-in-memory (CIM) architecture performs computations within memory bit-cell arrays, enhancing computational performance. Edge devices utilizing artificial intelligence (AI) address real-time problems and have established themselves as groundbreaking technology. The 8T structure proposed in this paper has strengths over other existing structures in that it better withstands environmental changes within the SRAM and consumes lower power during memory operation. This structure minimizes reliance on complex ADCs, instead utilizing a simplified voltage differential approach for multiply-and-accumulate (MAC) operations, which enhances both power efficiency and stability. Based on these strengths, it can achieve higher battery efficiency in AI edge devices and improve system performance. The proposed integrated circuit was simulated in a 90 nm CMOS process and operated on a 1 V supply voltage.

The effect of the total ionizing dose (TID) on the static random access memory (SRAM) is conducted on the 60Co radioactive source in the China Institute of Atomic Energy. The study explores the influence of the device process size, dose rate, temperature and total dose on TID. The results indicated that within a certain range, the dose rate had little influence on the TID of the device. The larger the characteristic size of the device, the greater TID effect, while the higher temperature, the weaker the total dose effect. In addition, the typical dose rate and the uniformity of the source are achieved. The research of the paper provide an insight into radiation hardening, particularly in the aerospace and the nuclear industries.

SRAM with high density CMOS technology is extremely sensitive to single event latch�up, so it is necessary to adopt corresponding protection strategies in space applications. For CTOS with reduced radiation resistance, circuit level protection becomes an important part to improve system reliability. A series of single event latch�up effect tests were carried out on CY62167DV30LL SRAM of CYPRESS Company by using laser single event effect test device. Through the linear fitting of the experimental results, the holding voltage of the SRAM is 1�5�1�6 V, and the holding current is 9�9�11�2 mA. According to the holding current, holding voltage, working current and working voltage, judge whether circuit level protection can be adopted. Two circuit level protection methods of power supply current limiting and divider resistor were proposed, and the value range of power supply current limiting and divider resistor were calculated quantitatively. In the previous literature, resistor is only used as a means of current limiting after latch�up trigger, which can not prevent the device from latch�up. It is found that the divider resistor can also achieve the purpose of preventing the latch�up under certain conditions. The two protection methods were verified by pulse laser test.

Computing-in-memory (CIM) is a promising approach to reduce latency and improve the energy efficiency of the multiply-and-accumulate (MAC) operation under a memory wall constraint for artificial intelligence (AI) edge processors. This paper proposes an approach focusing on scalable CIM designs using a new ten-transistor (10T) static random access memory (SRAM) bit-cell. Using the proposed 10T SRAM bit-cell, we present two SRAM-based CIM (SRAM-CIM) macros supporting multibit and binary MAC operations. The first design achieves fully parallel computing and high throughput using 32 parallel binary MAC operations. Advanced circuit techniques such as an input-dependent dynamic reference generator and an input-boosted sense amplifier are presented. Fabricated in 28 nm CMOS process, this design achieves 409.6 GOPS throughput, 1001.7 TOPS/W energy efficiency, and a 169.9 TOPS/mm2 throughput area efficiency. The proposed approach effectively solves previous problems such as writing disturb, throughput, and the power consumption of an analog to digital converter (ADC). The second design supports multibit MAC operation (4-b weight, 4-b input, and 8-b output) to increase the inference accuracy. We propose an architecture that divides 4-b weight and 4-b input multiplication to four 2-b multiplication in parallel, which increases the signal margin by $16\times $ compared to conventional 4-b multiplication. Besides, the capacitive digital-to-analog converter (CDAC) area issue is effectively addressed using the intrinsic bit-line capacitance existing in the SRAM-CIM architecture. The proposed approach of realizing four 2-b parallel multiplication using the CDAC is successfully demonstrated with a modified LeNet-5 neural network. These results demonstrate that the proposed 10T bit-cell is promising for realizing robust and scalable SRAM-CIM designs, which is essential for realizing fully parallel edge computing.

Combining the advantages of low-power consumption of static random access memory (SRAM) with high stability and nonvolatile of resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell was proposed in this paper. In order to solve the problem that data cannot be stored when SRAM is powered off, RRAM technology was introduced into SRAM to realize an SRAM with nonvolatile function. The differential mode was adopted to improve the data restoration speed. Meanwhile, a pre-decoding technology was proposed to realize fast address decoding, and a voltage-mode sensitive amplifier was used to achieve fast amplification of two bit lines, so as to improve the reading speed of the memory. An 8kb nvSRAM was implemented with a CMOS 28 nm 1P9M process. The simulation results show that when the power supply voltage was 0.9 V, the static/read/write noise margin was 0.35 V, 0.16 V and 0.41 V, respectively. The data storage time was 0.21 ns, and restoration time was 0.18 ns. The time for the whole system to read 1 bit of data was 5.2 ns.

An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dual-rail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one FBFET, and each transistor is located on the top tier and one on the bottom tier in a monolithic 3D integration, respectively. The electrical characteristics and operation of the NFBFET in the M3D-FBFET-SRAM cell were investigated using a TCAD simulator. For SRAM operation, the optimum doping profile of the NFBFET was used for non-turn-off characteristics. For the M3D-FBFET-SRAM cell, the operation of the SRAM and electrical coupling occurring between the top and bottom tier transistor were investigated. As the thickness of interlayer dielectric decreases, the reading ‘ON’ current decreases. To prevent performance degradation, two ways to compensate for current level were suggested.

Abstract This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.

The design and characteristics of double-gate (DG) junctionless (JL) devices are compared with the DG inversion-mode (IM) field effect transistors (FETs) at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso-V(th) for both n- and p-type of devices. The JL device shows lower drain-induced barrier lowering, steep subthreshold slope and lower OFF state current. For the first time, the authors demonstrate a pass gate (PG) logic, inverter circuit and static random access memory (SRAM) stability analysis using JL devices, rather than a complementary metal-oxide semiconductor (CMOS) configuration. They observed that transient response of JL PG configuration is similar to that of conventional CMOS PGs. JL inverter also shows similar transient characteristics with 25% reduction in delay and 12% improvement in 6 T SRAM cell stability compared with IMFETs, which shows large potential in digital circuit applications. The simulations were performed using coupled device-circuit methodology in ATLAS technology aided computer design (TCAD) mixed-mode simulator.