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A preliminary design of a compact first-level calorimeter trigger, implemented as a farm of local bit-serial systolic arrays, is presented. The bit-serial data representation allows higher processing rates and more compact designs than are possible when using parallel data. More functionality can be incorporated into the Application Specific Integra-ted Circuits (ASICs) that serve as the main processing elements. The trigger processor seeks local energy clusters, evaluates isolation criteria within the electromagnetic calorimeter and leakage into the hadron calorimeter in order to detect electrons. It uses cluster finding algorithms to identify jets and missing transverse energy to estimate neutrino energies. The processor output serves as decision support for the central first-level trigger and delivers region-of-interest positions to the second-level trigger. In its present form the trigger processor design relies on optical fibers to deliver the input data from the front-end modules and multi-chip modules (MCMs) to harbor the processing ASICs. The fact that the main part of the trigger processor can fit into one or two large crates suggests that the design is not limited by size nor is it strictly limited by cost but can be expanded to accommodate extended algorithms if these are found necessary. Extensive physics simulations will explore these possibilities.

A novel data acquisition model, the Front End Readout MIcrosystem (FERMI), finds application in high energy physics by enabling temporary calorimetric data storage. Digital filters help process the stored data, which is then monitored by a first-level trigger processor. Only the essential data is retained by the FERMI module, which is capable of serving nine channels simultaneously.

We present a digital solution to the front-end electronics for calorimetric detectors at future supercolliders based on high speed A/D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid will be used. This solution allows a new level of integration of complex analog and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. This type of VLSI multichip integration allows a high degree of programmability at both the function and the system level, and offers the possibility of customizing the microsystem with detector-specific functions.