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This paper proposes a low-complexity Mobile Display Digital Interface (MDDI) architecture. We implement and verify the proposed MDDI-host architecture on a System-on-Chip (SoC) platform with a 32-bit RISC CPU and a FPGA module. As a result of verification, the gate count of the MDDI host is reduced by about 50 % compared to that of the conventional parallel interface. And the bandwidth per pin of the MDDI host is 3 times more than that of a conventional parallel interface. Furthermore, the MDDI host that we implement includes the Advanced High-performance Bus (AHB) interface. Therefore, the proposed MDDI architecture is suitable for SoC platforms (1). Index Terms--Mobile display digital interface (MDDI), low power, low-complexity architecture, serial interface.

We present a surveillance camera architecture using a one-bit motion detection algorithm for portable applications. The conventional surveillance system requires too many components and is too complicated for portable applications. In this paper, we propose a simple surveillance camera architecture with a motion detector that can detect changes of an object within its surroundings for low-power and low-cost applications. The proposed motion-detection algorithm uses one-bit images which are selected using a binary search algorithm that is decided by varying the reference voltage. We verify all the functions of the motion detector through the use of a user interface program on an FPGA board. Experimental results are also presented (1). Index Terms--Portable security, Surveillance camera, Motion detection, CMOS image sensor (CIS).

This paper presents an adaptive repetitive control scheme for optical disk drivers to track a periodic reference signal with dynamic change in period. Periodic disturbances can be adequately attenuated using the concept of repetitive control, when provided with the known period. Optical disk drivers support various speeds. So optical disk drivers have a varying periodic disturbance. To deal with time varying periodic disturbances, a proposed repetitive controller is turned based on repetitive control to change the sampling frequency to follow the change of reference period. The proposed adaptive repetitive control consists of two portions, the repetitive controller and the frequency multiplier, where the former uses a varying sampler operating at a variable sampling rate maintained at fixed multiple times of the disturbance frequency and the latter generates a vary sampling .frequency based on the disturbance frequency. An adaptive repetitive control scheme is proposed, implemented on an experimental set of an optical disk driver. We have demonstrated the effectiveness of the proposed methods and the improvement of the random access time. Index Terms--Optical, Disk, Servo, Storage, Eccentric, repetitive control.

This paper proposes a dynamic eccentric error compensation architecture for the tracking follow controller of optical disk drivers. For enhancing the tracking performance in an optical disk drive servo system, it is essential to attenuate periodic disturbances which are caused by revolutions of the disk. Periodic disturbances can be attenuated using a Discrete Fourier Transform estimator with the known disturbance frequency provided by a motor driver. Optical disk drivers support various speeds. So optical disk drivers have a varying periodic disturbance. To deal with time varying periodic disturbances, a proposed eccentric error compensation controller is turned based on sinusoidal generator to follow the change of reference period. The disturbance estimator uses the Discrete Fourier Transform method that models the periodic disturbance. We present simulative and experimental results and show that the proposed control scheme enables a significant improvement of the tracking accuracy of the radial servomechanism and the random access time. We implement the proposed eccentric error controller on the System on Chip (SOC). Index Terms--Optical disk, Digital servo, Storage, Eccentric, Repetitive control, Tracking control, DFT.

This paper presents a Bluetooth System on Chip (SOC) architecture for multimedia applications. The SOC includes all necessary baseband-parts, RF-parts, a sub-band codec (SBC) and an application processor to achieve a Bluetooth specification v2.0+EDR (Enhanced Data Rate). Dual bus architecture is selected to improve data transmission efficiency between a baseband and a system bus. The receiver uses an optimized Low-IF (1.5MHz) architecture which is trade-off between power and performance on CMOS technology. The transmitter uses a direct up conversion architecture. This chip occupies a die size of 28[mm.sup.2] in a 0.18um CMOS. This chip and a flash memory are putted into multi chip package (MCP). The maximum current consumption of the total chip is 65mA at the TX mode. The internal supply voltages of RF- and digital-parts are 1.8V. First measurement results meet most of the Bluetooth specification v2.0+EDR and show the suitability of the presented single-chip concept (1). Index Terms--Bluetooth, direct conversion, low-IF frequency synthesizers, phase-locked loops, radio receivers, radio transmitters, single chip, system-on-chip (SoC), transceivers. Sub Band Codec (SBC).