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In this brief, we present a new VLSI architecture that can insert invisible or visible watermarks in images in the discret cosine transform domain. The proposed architecture incorporates low-power techniques such as dual voltage, dual frequency, and clock gating to reduce the power consumption and exploits pipelining and parallelism extensively in order to achieve high performance. The supply voltage level and the operating frequency are chosen for each module so as to maintain the required bandwidth and throughput match among the different modules. A prototype VLSI chip was designed and verified using various Cadence and Synopsys tools based on TSMC 0.25-[micro]m technology with 1.4 M transistors and 0.3 mW of estimated dynamic power. Index Terms--Discrete cosine transformation (DCT), low power design, spread-spectrum communication, still digital camera.

In low-power design for deep submicrometer and nanometer regimes, peak power, power fluctuation, average power, and total energy are equally important design constraints. In this paper, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power. The minimization schemes based on integer linear programming are developed for the design of datapaths that can function in three modes of operation: 1) single supply voltage and single frequency; 2) multiple supply voltages and dynamic frequency clocking (MVDFC); and 3) multiple supply voltages and multicycling. The techniques are evaluated by estimating the peak power consumption, the average power consumption and the power delay product of selected high level synthesis benchmark circuits for different resource constraints. Experimental results indicate that combining multiple voltages and dynamic frequency clocking as in the MVDFC scheme, yields significant reductions in the peak power, the average power, and the power delay product. Index Terms--Average power, datapath scheduling, dynamic clocking, high-level synthesis, multiple voltages, peak power.