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The relationship between subjective memory beliefs and suggestibility, compliance, false memories, and objective memory performance was studied in a community sample of young and middle-aged people (N = 142). We hypothesized that people with subjective memory problems would exhibit higher suggestibility and compliance levels and would be more susceptible to false recollections than those who are optimistic about their memory. In addition, we expected a discrepancy between subjective memory judgments and objective memory performance. We found that subjective memory judgments correlated significantly with compliance, with more negative memory judgments accompanying higher levels of compliance. Contrary to our expectation, subjective memory problems did not correlate with suggestibility or false recollections. Furthermore, participants were accurate in estimating their objective memory performance., There are large individual differences in how people evaluate their own memory. Although most of us tend to be quite optimistic about the power of our memory, some people believe [...]

Nonbinary turbo codes have many advantages over single-binary turbo codes, but their decoder implementations require much more memory, particularly for storing symbolic extrinsic information to be exchanged between two soft-input-soft-output (SISO) decoders. To reduce the memory size required for double-binary turbo decoding, this paper presents a new method to convert symbolic extrinsic information to bit-level information and vice versa. By exchanging bit-level extrinsic information, the number of extrinsic information values to be exchanged in double-binary turbo decoding is reduced to the same amount as that in single-binary turbo decoding. A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method, which reduces the total memory size by 20%. Index Terms--Double-binary turbo codes, extrinsic information, maximum a posteriori algorithm, turbo decoding.

To perform nontrivial, real-time computations on a sensory input stream, biological systems must retain a short-term memory trace of their recent inputs. It has been proposed that generic high-dimensional dynamical systems could retain a memory trace for past inputs in their current state. This raises important questions about the fundamental limits of such memory traces and the properties required of dynamical systems to achieve these limits. We address these issues by applying Fisher information theory to dynamical systems driven by time-dependent signals corrupted by noise. We introduce the Fisher Memory Curve (FMC) as a measure of the signal-to-noise ratio (SNR) embedded in the dynamical state relative to the input SNR. The integrated FMC indicates the total memory capacity. We apply this theory to linear neuronal networks and show that the capacity of networks with normal connectivity matrices is exactly 1 and that of any network of N neurons is, at most, N. A nonnormal network achieving this bound is subject to stringent design constraints: It must have a hidden feedforward architecture that superlinearly amplifies its input for a time of order N, and the input connectivity must optimally match this architecture. The memory capacity of networks subject to saturating nonlinearities is further limited, and cannot exceed [square root of N]. This limit can be realized by feedforward structures with divergent fan out that distributes the signal across neurons, thereby avoiding saturation. We illustrate the generality of the theory by showing that memory in fluid systems can be sustained by transient non-normal amplification due to convective instability or the onset of turbulence. Fisher information | fluid mechanics | network dynamics

A new total_zeros decoding method based on efficient memory architecture for variable-length code tables (VLCTs) is proposed in this paper. In general, a large amount of memory accesses are required for context-based adaptive variable-length coding (CAVLC) decoding in the H.264/AVC standard. It is an important issue for low-power implementation of mobile video applications because the memory access function results in considerable power consumption. Some distinctive features in the VLCTs of the total_zeros have been found through a careful analysis of the codewords. Efficient memory architecture and an advanced decoding are developed in order to remove redundant memory access. The simulation results show that the proposed method achieves an approximately 80%-90% memory access saving, compared with conventional decoding. Index Terms--Context-based adaptive variable-length coding (CAVLC) decoding, Exp-Golomb code, H.264/AVC, memory architecture, total_zeros, variable-length code table (VLCT).

We present a programming language, model, and logic appropriate for implementing and reasoning about a memory management system. We state semantically what is meant by correctness of a copying garbage collector, and employ a variant of the novel separation logics to formally specify partial correctness of Cheney's copying garbage collector in our program logic. Finally, we prove that our implementation of Cheney's algorithm meets its specification using the logic we have given and auxiliary variables. Categories and Subject Descriptors: D.2.7 [Software Engineering]: Distribution, Maintenance, and Enhancement--Documentation; F.3.1 [Logics and Meanings of Programs]: Specifying and Verifying and Reasoning about Programs--Assertions, Logics of programs, Specification techniques General Terms: Realiability, Theory, Verification Additional Key Words and Phrases: Separation logic, copying garbage collector, local reasoning

The cerebellum constitutes a vital part of the human brain system that possesses the capability to model highly nonlinear physical dynamics. The cerebellar model articulation controller (CMAC) associative memory network is a computational model inspired by the neuropbysiological properties of the cerebellum, and it has been widely used for control, optimization, and various pattern recognition tasks. However, the CMAC network's highly regularized computing structure often leads to the following: l) a suboptimal modeling accuracy, 21 poor memory utilization, and 3) the generalization-accuracy dilemma. Previous attempts to address these shortcomings have limited success and the proposed solutions often introduce a high operational complexity to the CMAC network. This paper presents a novel neurophysiologically inspired associative memory architecture named pseudo-self-evolving CMAC (PSECMAC) that nonuniformly allocates its computing cells to overcome the architectural deficiencies encountered by the CMAC network. The nonuniform memory allocation scheme employed by the proposed PSECMAC network is inspired by the cerebellar experience-driven synaptic plasticity phenomenon observed in the cerebellum, where significantly higher densities of synaptic connections are located in the frequently accessed regions. In the PSECMAC network, this biological synaptic plasticity phenomenon is emulated by employing a data-driven adaptive memory quantization scheme that defines its computing structure. A neighborhood-based activation process is subsequently implemented to facilitate the learning and computation of the PSECMAC structure. The training stability of the PSECMAC network is theoretically assured by the proof of its learning convergence, which will be presented in this paper. The performance of the proposed network is subsequently benchmarked against the CMAC network and several representative CMAC variants on three real-life applications, namely, pricing of currency futures option, banking failure classification, and modeling of the glucose-insulin dynamics of the human glucose metabolic process. The experimental results have strongly demonstrated the effectiveness of the PSECMAC network in addressing the architectural deficiencies of the CMAC network by achieving significant improvements in the memory utilization, output accuracy as well as the generalization capability of the network. Index Terms--Associative memory, brain inspired, cerebellar model articulation controller (CMAC), cerebellum, learning convergence, multiresolution, neural networks, pseudo-self-evolving CMAC (PSECMAC).

High performance clusters are being configured specially to give data centers that require extreme performance and the processing power they need. When the data is accessed across clusters the data latency time has significant impact on the performance. In the literature it is given that memory and I/O have become the new bottleneck, instead of processing power in achieving efficient load balance at higher performance for cluster computer systems. Initial job placement and load balancing are the key aspects affecting the performance. The proposed technique combines data access patterns, memory and CPU utilization and locality of memory to consider as load metric in the load balancing aspect across cluster. A scheduling algorithm based on this metric has been proposed to dynamically balance the load in the cluster. Initial job placement for a job in the cluster considers data access patterns and for load balance aspect metric constitutes CPU, memory utilization including locality of memory. Experimental results shown performance improvement to considerable levels with the implementation of the concept, specifically when the cost of data access from other clusters is higher and is proportionate to the amount of data. Keywords: High Performance Cluster Computing, Load Balancing, Memory Management, Load Metric, Initial Job Placement., INTRODUCTION A cluster computer is a collection of computers interconnected with a High-speed network technology. The individual computers can be PCs or workstations. Ideally, a cluster works as an integrated [...]

The packed-memory array (PMA) is a data structure that maintains a dynamic set of N elements in sorted order in a [THETA](N)-sized array. The idea is to intersperse [THETA](N) empty spaces orgaps among the elements so that only a small number of elements need to be shifted around on an insert or delete. Because the elements are stored physically in sorted order in memory or on disk, the PMA can be used to support extremely efficient range queries. Specifically, the cost to scan L consecutive elements is O(1 + L/B) memory transfers. This article gives the first adaptive packed-memory array (APMA), which automatically adjusts to the input pattern. Like the traditional PMA, any pattern of updates costs only O([log.sup.2] N) amortized element moves and O(1 + ([log.sup.2] N)/B) amortized memory transfers per update. However, the APMA performs even better on many common input distributions achieving only O(logN) amortized element moves and O(1 + (log N)/B) amortized memory transfers. The article analyzes sequential inserts, where the insertions are to the front of the APMA, hammer inserts, where the insertions "hammer" on one part of the APMA, random inserts, where the insertions are after random elements in the APMA, and bulk inserts, where for constant [alpha] [member of] [0, 1], [N.sup.[alpha]] elements are inserted after random elements in the APMA. The article then gives simulation results that are consistent with the asymptotic bounds. For sequential insertions of roughly 1.4 million elements, the APMA has four times fewer element moves per insertion than the traditional PMA and running times that are more than seven times faster. Categories and Subject Descriptors: D.1.0 [Programming Techniques]: General; E.1 [Data Structures]: Arrays--Lists, stacks, queues; E.5 [Files]--Sorting/searching; H.3.3 [Information Storage and Retrieval]: Information Search and Retrieval General Terms: Algorithms, Experimentation, Performance, Theory Additional Key Words and Phrases: Adaptive packed-memory array, cache oblivious, locality preserving, packed-memory array, range query, rebalance, sequential file maintenance, sequential scan, sparse array

We present a unified mathematical framework for analyzing the tradeoffs between parallelism and storage allocation within a parallelizing compiler. Using this framework, we show how to find a good storage mapping for a given schedule, a good schedule for a given storage mapping, and a good storage mapping that is valid for all legal (one-dimensional affine) schedules. We consider storage mappings that collapse one dimension of a multidimensional array, and programs that are in a single assignment form and accept a one-dimensional affine schedule. Our method combines affine scheduling techniques with occupancy vector analysis and incorporates general affine dependences across statements and loop nests. We formulate the constraints imposed by the data dependences and storage mappings as a set of linear inequalities, and apply numerical programming techniques to solve for the shortest occupancy vector. We consider our method to be a first step towards automating a procedure that finds the optimal tradeoff between parallelism and storage space. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors--compilation; optimization; memory management General Terms: Languages Additional Key Words and Phrases: Automatic parallelization, affine scheduling, storage optimization, occupancy vectors, polyhedral model, affine recurrence equations ACM Reference Format: DOI = 10.1145/1286821.1286825 http://doi.acm.org/10.1145/1286821.1286825

The impact of abrupt-onset cues on memory search was investigated, where the abrupt-onset cue was a valid (Experiment 1), random (Experiment 2), or irrelevant (Experiment 3) predictor of the location containing the test probe. In Experiment 4, the abrupt-onset cue either preceded or followed the test probe. Sternberg-like functions were obtained in Experiments 1 and 2, with the effects of the abrupt-onset cue localized primarily in the intercept rather than the slope. Experiment 3 demonstrated that a spatially separated and irrelevant abrupt-onset cue increased latency even when all memory probes occurred at the fixation point. In Experiment 4, the robust impact of an abrupt-onset cue vanished, regardless of stimulus onset asynchrony, when it followed the target. We concluded that abrupt-onset cues captured attention regardless of their predictability, manifested as a delaying of search. However, once attention was captured by the target, a subsequent abrupt-onset stimulus had no effect. These results were discussed in terms of diffuse attention and contingent capture models of attention.

This paper deals with partitions of a discrete set 5 of points in a d-dimensional space, by h parallel hyperplanes. Such partitions are in a direct correspondence with multilinear threshold functions which appear in the theory of neural networks and multivalued logic. The characterization (encoding) problem is studied. We show that a unique characterization (encoding) of such multilinear partitions of [S = [{0. 1 ..... m - 1}.sup.d] is possible within O( h . [d.sup.2] + log m ) bit rate per encoded partition. The proposed characterization (code) consists of (d + 1) * (h + 1 ) discrete moments having the order no bigger than 1. The obtained bit rate is evaluated depending on the mutual relations between h. d, and m. The optimality is reached in some cases. Index Terms--Multilinear partitions, multilevel threshold function, neural networks, discrete moments, encoding, storage complexity.

Most existing methods for HPA predistortion with memory effects are based on polynomial or indirect learning structures. Few papers concern about the memory predistortion with LUT based techniques. Based on the previously presented method, we propose an improved two-dimensional LUT indexing method for HPA predistortion with memory. Computer simulations and corresponding analysis demonstrate that the proposed method has more effective predistortion capabilities but lower computational complexity. Index Terms--HPA, LUT, memory effects, predistortion.

With the diverging improvements in CPU speeds and memory access latencies, detecting and removing memory access bottlenecks becomes increasingly important. In this work we present METRIC, a software framework for isolating and understanding such bottlenecks using partial access traces. METRIC extracts access traces from executing programs without special compiler or linker support. We make four primary contributions. First, we present a framework for extracting partial access traces based on dynamic binary rewriting of the executing application. Second, we introduce a novel algorithm for compressing these traces. The algorithm generates constant space representations for regular accesses occurring in nested loop structures. Third, we use these traces for offline incremental memory hierarchy simulation. We extract symbolic information from the application executable and use this to generate detailed source-code correlated statistics including per-reference metrics, cache evictor information, and stream metrics. Finally, we demonstrate how this information can be used to isolate and understand memory access inefficiencies. This illustrates a potential advantage of METRIC over compile-time analysis for sample codes, particularly when interprocedural analysis is required. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors---Compilers; optimization; B.3.2 [Memory Structures]: Design Styles--Cache memories General Terms: Algorithms, Languages, Performance Additional Key Words and Phrases: Dynamic binary rewriting, program instrumentation, data trace generation, data trace compression, cache analysis

Write buffering is one of many successful mechanisms that improves the performance and scalability of multiprocessors. However, it leads to more complex memory system behavior, which cannot be described using intuitive consistency models, such as Sequential Consistency. It is crucial to provide programmers with a specification of the exact behavior of such complex memories. This article presents a uniform framework for describing systems at different levels of abstraction and proving their equivalence. The framework is used to derive and prove correct simple specifications in terms of program-level instructions of the SPARC total store order and partial store order memories. The framework is also used to examine the SPARC relaxed memory order. We show that it is not a memory consistency model that corresponds to any implementation on a multiprocessor that uses write-buffers, even though we suspect that the SPARC version 9 specification of relaxed memory order was intended to capture a general write-buffer architecture. The same technique is used to show that Coherence does not correspond to a write-buffer architecture. A corollary, which follows from the relationship between Coherence and Alpha, is that any implementation of Alpha consistency using write-buffers cannot produce all possible Alpha computations. That is, there are some computations that satisfy the Alpha specification but cannot occur in the given write-buffer implementation. Categories and Subject Descriptors: C.0 [General]: Modeling of computer architecture; C.1.4 [Processor Architecture]: Parallel Architectures--Distributed architectures; F.1.2 [Computation by Abstract Devices]: Modes of Computation--Parallelism and concurrency General Terms: Theory Additional Key Words and Phrases: Memory consistency framework, write-buffer architectures, SPARC multiprocessors, total store order, partial store order, relaxed memory order, sequential consistency, alpha, coherence DOI = 10.1145/1189736.1189737

A simple mechanism to increase the utilization of a small trace cache, and simultaneously reduce its power consumption, is presented in this article. The mechanism uses selective storage of traces (filtering) that is based on a new concept in computer architecture: random sampling. The sampling filter exploits the "hot/cold trace" principle, which divides the population of traces into two groups. The first group contains "hot traces" that are executed many times from the trace cache and contribute the majority of committed instructions. The second group contains "cold traces" that are rarely executed, but are responsible for the majority of writes to an unfiltered cache. The sampling filter selects traces without any prior knowledge of their quality. However, as most writes to the cache are of "cold traces" it statistically filters out those traces, reducing cache turnover and eventually leading to higher quality traces residing in the cache. In contrast with previously proposed filters, which perform bookkeeping for all traces in the program, the sampling filter can be implemented with minimal hardware. Results show that the sampling filter can increase the number of hits per build (utilization) by a factor of 38, reduce the miss rate by 20% and improve the performance-power efficiency by 15%. Further improvements can be obtained by extensions to the basic sampling filter: allowing "hot traces" to bypass the sampling filter, combining of sampling together with previously proposed filters, and changing the replacement policy in the trace cache. Those techniques combined with the sampling filter can reduce the miss rate of the trace cache by up to 40%. Although the effectiveness of the sampling filter is demonstrated for a trace cache, the sampling principle is applicable to other micro-architectural structures with similar access patterns. Categories and Subject Descriptors: B.3.3 [Memory Structures]: Performance Analysis and Design Aids; C.1.1 [Processor Architectures]: Single Data Stream Architectures General Terms: Performance; Measurement Additional Key Words and Phrases: Trace cache, sampling filter, power dissipation, cache utilization DOI = 10.1145/1189736.1189739

Pretenuring can reduce copying costs in garbage collectors by allocating long-lived objects into regions that the garbage collector will rarely, if ever, collect. We extend previous work on pretenuring as follows: (1) We produce pretenuring advice that is neutral with respect to the garbage collector algorithm and configuration. We thus can and do combine advice from different applications. We find for our benchmarks that predictions using object lifetimes at each allocation site in Java programs are accurate, which simplifies the pretenuring implementation. (2) We gather and apply advice to both applications and Jikes RVM, a compiler and runtime system for Java written in Java. Our results demonstrate that building combined advice into Jikes RVM from different application executions improves performance, regardless of the application Jikes RVM is compiling and executing. This build-time advice thus gives user applications some benefits of pretenuring, without any application profiling. No previous work uses profile feedback to pretenure in the runtime system. (3) We find that application-only advice also consistently improves performance, but that the combination of build-time and application-specific advice is almost always noticeably better. (4) Our same advice improves the performance of generational, Older First, and Beltway collectors, illustrating that it is collector neutral. (5) We include an immortal allocation space in addition to a nursery and older generation, and show that pretenuring to immortal space has substantial benefit. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors--Memory management (garbage collection) General Terms: Algorithms, Languages, Performance Additional Key Words and Phrases: Garbage collection, pretenuring, lifetime prediction, profiling ACM Reference Format: Blackburn, S. M., Hertz, M., McKinley, K. S., Moss, J. E. B., and Yang, T., 2007. Profile-based pretenuring. ACM Trans. Program. Lang. Syst. 29, 1, Article 2 (January 2007), 57 pages. DOI = 10.1145/1180475.1180477 http://doi.acm.org/10.1145/1180475.1180477.

The analysis of the effect of interaction with a virtual object, on the true and false memories of consumers, is presented.

Improvements in 5- and 7-year-olds' acquisition and retention of related concept pairings were examined when additional similarities and differences between pair members were provided. Using a standard paired-associate learning paradigm, children learned 18 related picture pairs; some of the children either were given or produced additional similarities or differences between pair members at the time of learning. Three weeks after learning was complete, children attempted to recall the pairs. Using a model to determine the storage and retrieval loci of these effects, the results showed that (a) all children benefited from self-generated elaborations, regardless of whether these were similarities or differences, and these benefits were storage related, and (b) difference elaborations improved children's retention regardless of whether they were self- or experimenter-generated, and these effects were primarily retrieval based. These results are consistent with theories that (a) view retrieval as the locus of distinctiveness effects and (b) view storage as the locus of self-generated memory improvements. Keywords: distinctiveness effects in memory, memory development, long-term retention, mathematical modeling

A new n-process algorithm for mutual extension that is correct for processor Consistency-Goodman's version (PC-G) and achieves the bound for any n, is presented. While Peterson's algorithm, which for two processes uses one multiwire and two single-writer variables, and establishes that this bound is tight, is fair, this extension in arbitrary n is not fair.

A large portion of silicon area and the energy consumed by the Viterbi decoder (VD) is dedicated to the survivor memory and the access operations associated with it. In this work, an efficient pre-traceback architecture for the survivor-path memory unit (SMU) of high constraint length VD targeting wireless communication applications is proposed. Compared to the conventional traceback approach which is based on three kinds of memory access operations: decision bits write, traceback read, and decode read, the proposed architecture exploits the inherent parallelism between the decision bit write and decOde traceback operation by introducing pre-traceback operation. Consequently, the proposed pre-traceback approach reduces the survivor memory read operations by 50%. As a result of the reduction of the memory access operations, compared to the conventional 2-pointer traceback algorithm, the size of the survivor memory as well as the decoding latency is reduced by as much as 25%. Implementation results show that the pre-traceback architecture achieves up to 11.9% energy efficiency and 21.3% area saving compared to the conventional traceback architecture for typical wireless applications. Index Terms--Survivor-path memory unit (SMU), traceback, Viterbi decoder (VD).

In systems that support garbage collection, a tension exists between collecting garbage too frequently and not collecting it frequently enough. Garbage collection that occurs too frequently may introduce unnecessary overheads at the risk of not collecting much garbage during each cycle. On the other hand, collecting garbage too infrequently can result in applications that execute with a large amount of virtual memory (i.e., with a large footprint) and suffer from increased execution times due to paging. In this article, we use a large set of Java applications and the highly tuned and widely used Boehm-Demers-Weiser (BDW) conservative mark-and-sweep garbage collector to experimentally examine the extent to which the frequency of garbage collection impacts an application's execution time, footprint, and pause times. We use these results to devise some guidelines for controlling garbage collection and heap growth in a conservative garbage collector in order to minimize application execution times. Then we describe new strategies for controlling garbage collection and heap growth that impact not only the frequency with which garbage collection occurs but also the points at which it occurs. Experimental results demonstrate that when compared with the existing approach used in the standard BDW collector, our new strategy can significantly reduce application execution times. Our goal is to obtain a better understanding of how to control garbage collection and heap growth for an individual application executing in isolation. These results can be applied in a number of high-performance computing and server environments, in addition to some single-user environments. This work should also provide insights into how to make better decisions that impact garbage collection in multiprogrammed environments. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors--Memory management (garbage collection) General Terms: Algorithms, Experimentation, Languages, Measurement, Performance Additional Key Words and Phrases: Garbage collection, heap growth, implementation, Java, memory management, performance measurement, programming languages

The characteristics of ScalaBLAST are illustrated which accommodates very large databases and which scales linearly to thousands of processors on distributed memory and shared memory architectures. This approach solves scalability problems and memory limitations, the two main shortcomings of the existing application and vastly improves time-to-solution for large sequence alignment performed on newly sequenced organisms and also on organisms like human.

A two-stage exact algorithm called PAGEB, which is proposed to solve spare allocation problems efficiently, is presented. The experimental results indicate that the proposed algorithm is very efficient in terms of speed and memory requirement, which might also be useful for problems modeled as constraint bipartite vertex cover problems.