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This paper presents several comprehensive and novel circuit techniques that can be efficiently applied to low-voltage (LV) high-speed reset-opamp (RO) and switched-opamp (SO) in LV switched-capacitor circuits. The first, designated as virtual-ground common-mode (CM) feedback with output CM error correction, allows the design of fully differential RO circuits that could only be traditionally implemented before in pseudo-differential mode, and it leads to considerable savings of half of the opamps' power. The second, uses a crossed-coupled passive sampling interface to avoid the extra track-and-reset stages as required in both RO and SO circuits, further saving one front-end opamp's power. The third, employs a voltage-controlled level-shifting (LS) technique that utilizes the charge redistribution property to process the CM LS in an LV environment, avoiding the degradation of the feedback factor by the use of extra LS circuits. Finally, the fourth, the LV finite-gain compensation technique allows the use of low-gain high-speed single-stage amplifier in contrast to the conventional high-gain, low-speed two-stage opamp to achieve a high-speed operation in both RO and SO circuits. Without any clock boosting or bootstrap circuits, all of the above techniques can be applied in LV applications without any floating switches limitations. Measurement results of a 1.2-V 10-bit 60 MS/s pipelined analog-digital converter in 0.18-[micro]m CMOS with RO are presented to verify the effectiveness of the proposed techniques, achieving a signal-to-noise distortion ratio of 55.2 dB with 85-mW power consumption. Index Terms--Common-mode feedback (CMFB), finite-gain compensation (FGC), low voltage (LV), reset-opamp (RO), switched-capacitor (SC) circuits, switched-opamp (SO).

Time interleaving is one of the most efficient techniques employed in the design of high-speed sampled-data systems. However, the mismatches appearing among different channels will create distortion tones that will degrade the system performance. This paper presents a detailed analysis of the effect of sampling bandwidth mismatches in the statistical behavior of time-interleaved sampling systems. Closed-form and handy signal-to-noise distortion ratio formulas will also be derived which allow quick evaluation of the system performance, and the MATLAB simulations are provided in order to verify the effectiveness of those formulas. Finally, the corresponding design procedure extracted from the formulas will be further addressed through a design example. Index Terms--Bandwidth mismatches, sampled-data systems, time-interleaved (TI) analog-to-digital converter (ADC).

Two circuit techniques adopted in the design of an embedded programmable-gain amplifier (PGA) for very low-voltage (LV) wireless local-area network systems are presented. A switched-current-resistor (SCR) technique minimizes the bandwidth variation and the transient in gain tuning by stabilizing, concurrently, the PGA's feedback factor and quiescent-operating point. Another technique, inside-opamp dc-offset canceller (DOC), embeds inside the PGA's opamp a subthreshold-biased [G.sub.m]-C integrator for extracting its output dc-offset, while negatively feeding the correction (current) signal back to the opamp at an inherent low-impedance node. The resultant main benefits are: 1) the chip area, for realizing the large time constant in dc-offset extraction, is very small and 2) the lower cutoff of the PGA and the DOC-induced nonlinearity and noise are all suppressed by an amount of the loop gain in closed-loop formation. A 1-V three-stage 52-dB gain range PGA reinforcing such two techniques was designed and fabricated in a 3.3-V 0.35-[micro]m CMOS process. It consumes 7.4 mW of power while measuring < 0.2-[micro]s gain-switching transient and +8.4 dBm IIP3. The means of the lower and upper -3-dB cutoffs (averaged over 52-dB gain steps) are 2.25 kHz and 17.1 MHz, respectively. Index Terms--CMOS, constant bandwidth (BW), dc-offset canceller (DOC), low voltage (LV), programmable-gain amplifier (PGA), transient, wireless local-area network (WLAN).

This paper starts with a review of the prevailing channel-selection techniques utilized so far in the design of wireless transceiver analog front-ends before describing a novel two-step channel-selection technique, which handles the traditionally unwanted image, in radio frequency-to-intermediate frequency (RF-to-IF) or IF-to-RF frequency conversion, as a useful adjacent channel of the desired one, and selects deliberately either of them from IF to baseband (or baseband to IF). Thus, one more channel-selection possibility is created for both low-IF receivers and two-step-up transmitters. The consequential benefits of introducing channel selection at IF consist of two. First, many design specifications (such as phase noise and settling time) of the RF frequency synthesizer and local oscillator can be substantially relaxed. Second, a low-iF/zero-iF reconfigurable receiver and a direct-up/two-step-up reconfigurable transmitter can be synthesized to match better with narrowband-wideband-mixed multistandard systems. The operating principles of such architectures are presented in easy-to-understand complex-signal spectral-flow illustrations, and their practicability is demonstrated in the design of a Bluetooth/IEEE 802.11FH/HomeRF multistandard receiver. SPECTRE simulation results validate the reconfigurable functionalities mainly implemented by a triple-mode channel-select filter and a multifunctional sampling-mixer scheme. Index Terms--Analog front-end (AFE), Bluetooth, channel selection, Home RF, intermediate frequency (IF), IEEE 802.11 WLANs, low-iF, multistandard, narrowband, receiver, radio frequency (RF), transmitter, transceiver, wideband, zero-IF.

This paper proposes improved switched-capacitor (SC) interpolators using a novel sampling technique which eliminates the undesired distortion due to the sample-and-hold shaping effect at the lower input sampling rate. Such a sampling technique not only leads to a precise analog interpolation, as its digital counterpart does, but also allows to simplify the design procedures and resulting SC circuit implementations. Different circuit topologies with both finite- and infinite-impulse response characteristics are developed, respectively, for low- and high-selectivity filtering. Practical implementation issues are discussed with respect to capacitance ratio mismatches, as well as finite gain, bandwidth, and offset sensitivity effects of operational amplifiers. Besides detailed computer-based analyses, experimental results obtained from discrete component prototypes are also presented to demonstrate the proposed circuits. Index Terms--CMOS analog integrated circuits, filtering, integrated circuit design, interpolation, multirate signal processing, sampled data circuits, signal sampling/reconstruction, switched-capacitor filters.