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The backbone of modern computing systems rely on two key things: logic and memory, and while computing power hasseen tremendous advancements through scaling of the fundamental building block – the transistor, memory access hasn’tevolved as rapidly, leading to significant memory-bound systems. Additionally, the rapid evolution of machine learningand deep neural network (DNN) applications, has exposed the fundamental limitations of the traditional von Neumanncomputing architecture, due to its heavy reliance on memory access. The physical separation between the computing unitand the memory in von Neumann architectures is limiting performance and energy efficiency. A promising solution toaddress these challenges is the development of emerging non-volatile memory technologies that provide significant scalingand integration possibilities, fast switching speeds, and highly energy-efficient operations. Additionally, by integrating“memory resistors” (memristors) in large crossbar arrays, the computation can take place in-memory which can resolve thebottleneck in traditional von Neumann architectures.This thesis investigates the implementation of ferroelectric HfO2 in ferroelectric tunnel junctions (FTJs) and ferroelectricfield effect transistors (FeFETs) as potential candidates for emerging non-volatile memories and memristors.Initially, the thesis focuses on the integration of ferroelectric HfO2 onto the high mobility III-V semiconductor InAs forthe fabrication of metal-oxide-semiconductor (MOS) capacitors. Moreover, optimization of the processing conditions on thecritical interface between the semiconductor and high-k oxide is extensively studied using both electrical characterization andsynchrotron radiation techniques. After optimization of the annealing treatment and top electrode texturing, the fabricationof vertical InAs nanowire FeFETs is successfully implemented. The FeFET shows encouraging initial results with limitationssolvable by further process engineering.The

In this work, we evaluate the importance of the postmetallization annealing (PMA) temperature on the performance of HfxZr1−xO2-based ferroelectric tunnel junctions (FTJs). Our results indicate a significant difference in tunneling electroresistance (TER) ratio and endurance, depending on the PMA temperature despite negligible variations in remanent polarization. We conclude that the minimization of conductive oxide defect states is central to achieve high performance. Through carefully optimized PMA conditions, we demonstrate FTJs with a TER = 3 and low mean cycle-to-cycle variation of < 1.5% combined with at least 16 separable conductance states providing a 4-bit resolution analog FTJ.

We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.