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Improvement of current drive in n- and p-type silicon junctionless metal-oxide-semiconductor-field-effect-transistors (MOSFETs) using strain is demonstrated. Junctionless transistors have heavily doped channels with doping concentrations in excess of 10(19) cm(-3) and feature bulk conduction, as opposed to surface channel conduction. The extracted piezoresistance coefficients are in good agreement with the piezoresistive theory and the published coefficients for bulk silicon even for 10 nm thick silicon nanowires as narrow as 20 nm. These experimental results demonstrate the possibility of enhancing mobility in heavily doped silicon junctionless MOSFETs using strain technology. (C) 2010 American Institute of Physics. [doi:10.1063/1.3474608]

In this paper, we analyse for the first time the effectiveness of the quasi-double gate (QDG) method for performance prediction of short channel double gate (DG) silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs) over the entire operating region. An analytical model has been developed to explain the abnormally low values (<< 60 mV/decade) of subthreshold slope that are obtained in QDG devices. We extract the low field mobility (mu(o)), subthreshold slope (S), threshold voltage (V-th), transconductance-to-drain current ratio (g(m)/I-ds) and peak transconductance (g(m))(max) in linear and saturation regions for deep. submicron QDG devices. We demonstrate that the QDG method can accurately predict g(m)/I-ds, (gm)max and mu(o) values for a deep submicron real DG device in the linear and strong inversion regions.

A detailed analysis of static and dynamic characteristics of deep submicron double and single gate SOI MOSFETs is presented, based on 2D numerical simulations for high frequency analog applications. Results show that although DG MOSFET offers excellent performance with respect to short channel immunity and higher transconductance, it offers nearly two times the value of gate-to-source capacitance as compared to SG devices, thus limiting the cut-off frequency at higher gate voltages. At ultra short channel lengths and low gate overdrive voltages, DG devices show a significant improvement in cut-off frequency compared to SG devices, thus presenting DG nanotransistors as potential candidates for analog microwave applications.

An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in double gate (DG) silicon-on-insulator (SOI) MOSFETs. Based on modeling, 2D simulation and experimental results, we show DG MOSFETs with laterally asymmetric channel engineering can achieve high values of saturation drain current, exceptionally high values of Early voltage (> 1600 V) and intrinsic DC gain of 70-80 dB for L-eff = 1.64 mum, well in excess of those reported so far. Results of GC DG MOSFETs have also been compared with experimental and simulated data of uniformly doped double and single gate (SG) SOI MOSFETs. The analysis takes into account the effect of length and doping of the high and low doped regions to develop a compact model suitable for device design. The results of analytical model agree well with experimental and simulation data. We propose design guidelines for overall optimum performance of GC DG MOSFETs for realizing future high performance analog circuits. (C) 2004 Elsevier Ltd. All rights reserved.

This work introduces the use of Gate-All-Around SOI MOSFETs using the Graded-Channel (GC) architecture for analog circuits and compare their performance with both conventional and GC single-gate (SG) fully depleted (FD) SOI transistors. It is demonstrated that Graded-Channel GAA MOSFETs can provide extremely improved Early voltage and high transconductance and drive current in comparison to the conventional GAA and SG FD MOSFETs with similar dimensions.

This work studies the use of graded-channel profile on double gate SOI MOSFETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio.

Based on analytical modeling, 2D simulation and experimental results, this work demonstrates the potential benefits of using laterally asymmetric channel design over uniform doping in DG SOI MOSFETs for achieving excellent analog performance. We show that the asymmetric channel design in DG MOSFETs makes it possible to achieve a DC gain of 80 dB, an Early voltage of over 1200 V and nearly ideal values (/spl sim/38 V/sup -1/) of transconductance-to-current ratio for L/sub eff/ = 1.64 /spl mu/m, well in excess of those reported so far. Analysis shows new opportunities for realising future high performance analog circuits with GC DG MOSFETs.