Search

Current practice in parameter space exploration in euclidean space is dominated by randomized sampling or design of experiment methods. The biggest issue with these methods is not keeping track of what part of parameter space has been explored and what has not. In this context, we utilize the geometric learning of explored data space using modern machine learning methods to keep track of already explored regions and samples from the regions that are unexplored. For this purpose, we use a modified version of a robust random-cut forest along with other heuristic-based approaches. We demonstrate our method and its progression in two-dimensional Euclidean space but it can be extended to any dimension since the underlying method is generic.

Non-PR, IFPRI2; CRP2; 5 Strengthening Institutions and Governance; Capacity Strengthening; DCA, DSGD; PIM, CGIAR Research Program on Policies, Institutions, and Markets (PIM), Investing in farmers – or agriculture human capital – is crucial to addressing challenges in our agri-food systems. A global study carried out by the FAO Investment Centre and the International Food Policy Research Institute, with support from the CGIAR Research Programme on Policies, Institutions and Markets and the FAO Research and Extension Unit, looks at agriculture human capital investments, from trends to promising initiatives. One of the nine featured case studies is the Jharkhand Opportunities for Harnessing Rural Growth Programme in India. This case explores investment in developing the human capital of women livestock farmers as certified master trainers and community service providers known as Ajeevika Pashu Sakhi (APS). The livestock farmers were strategically identified, trained and coached as APSs to provide doorstep technical, marketing and risk reduction support to women livestock farmers. The APSs were supported by certified master trainers. The APS model enhanced the economic and social well-being of rural poor women working as livestock farmers and APSs. This publication is part of the Country Investment Highlights series under the FAO Investment Centre's Knowledge for Investment (K4I) programme.

Effect of single walled carbon nanotubes (SWCNT) in ferroelectric liquid crystal (FLC) geometry has been studied for low and high concentrations of dopant. The results are compared with the characteristics of pure FLC system. An appreciable change in dielectric permittivity, relaxation behavior and other vital parameters has been observed for SWCNT doped FLC system, which shows the adaptability of carbon nanotubes with that of pure FLC molecule. Under high electric field, highly concentrated SWCNT doped FLC shows enormously large values of dielectric loss. This is due to the high conductivity of SWCNT at higher electric field. Interestingly, such effect is not much prominent for the low concentration of the SWCNT doped FLC system. © 2011 Elsevier B.V. All rights reserved.

Effect of single walled carbon nanotubes (SWCNT) in ferroelectric liquid crystal (FLC) geometry has been studied for low and high concentrations of dopant. The results are compared with the characteristics of pure FLC system. An appreciable change in dielectric permittivity, relaxation behavior and other vital parameters has been observed for SWCNT doped FLC system, which shows the adaptability of carbon nanotubes with that of pure FLC molecule. Under high electric field, highly concentrated SWCNT doped FLC shows enormously large values of dielectric loss. This is due to the high conductivity of SWCNT at higher electric field. Interestingly, such effect is not much prominent for the low concentration of the SWCNT doped FLC system. © 2011 Elsevier B.V. All rights reserved.

In this paper, a simple low temperature (600 degrees C) polysilicon technology called the Elevated Channel TFT (ECTFT) technology is reported. This technology provides all the necessary components needed for the ultimate goal of building large area microelectronic systems on glass. These components include high current digital devices, kink-free analog devices, large storage capacitance with reduced area, high current driver devices and efficient memory devices. With this technology, small or medium size display systems on glass can be realized.

Leakage current mechanism in polysilicon TFTs fabricated on a non-uniform film is investigated. The approach utilizes test structures which have non-uniform film thickness at the drain, source and channel regions. An order of magnitude reduction in leakage current at high drain bias is observed in the thick drain TFT structure compared to the thin drain structure. The improvement on the leakage current is due to the reduction in electric field at the thicker drain. The electric field reduction in the thick drain structure is verified using two-dimensional simulations. The influence of the electric field on the anomalous leakage current is investigated with the grain boundary trapping effects separated out.

Leakage current mechanism in polysilicon TFTs fabricated on a non-uniform film is investigated. The approach utilizes test structures which have non-uniform film thickness at the drain, source and channel regions. An order of magnitude reduction in leakage current at high drain bias is observed in the thick drain TFT structure compared to the thin drain structure. The improvement on the leakage current is due to the reduction in electric field at the thicker drain. The electric field reduction in the thick drain structure is verified using two-dimensional simulations. The influence of the electric field on the anomalous leakage current is investigated with the grain boundary trapping effects separated out.

In this paper, a simple low temperature (600 degrees C) polysilicon technology called the Elevated Channel TFT (ECTFT) technology is reported. This technology provides all the necessary components needed for the ultimate goal of building large area microelectronic systems on glass. These components include high current digital devices, kink-free analog devices, large storage capacitance with reduced area, high current driver devices and efficient memory devices. With this technology, small or medium size display systems on glass can be realized.

Leakage current mechanism in polysilicon TFTs fabricated on a non-uniform film is investigated. The approach utilizes test structures which have non-uniform film thickness at the drain, source and channel regions. An order of magnitude reduction in leakage current at high drain bias is observed in the thick drain TFT structure compared to the thin drain structure. The improvement on the leakage current is due to the reduction in electric field at the thicker drain. The electric field reduction in the thick drain structure is verified using two-dimensional simulations. The influence of the electric field on the anomalous leakage current is investigated with the grain boundary trapping effects separated out.

In this paper, a simple low temperature (600 degrees C) polysilicon technology called the Elevated Channel TFT (ECTFT) technology is reported. This technology provides all the necessary components needed for the ultimate goal of building large area microelectronic systems on glass. These components include high current digital devices, kink-free analog devices, large storage capacitance with reduced area, high current driver devices and efficient memory devices. With this technology, small or medium size display systems on glass can be realized.

The effects of offset region doping on the high voltage characteristics of polycrystalline silicon conductivity modulated thin film transistors (CMTFT) are investigated. A non-critical implant can be used to reduce the forward voltage drop of the transistor for longer offset region devices, and a favourable trade-off between the forward voltage drop and leakage current can be obtained by using the offset region doping. An 8 times increase in drain to source current in doped CMTFT devices causes only a 30% increase in leakage current compared to the undoped devices.

The effects of drift region doping on the high voltage (up to 100V) characteristics of the Conductivity Modulated Thin Film Transistor is investigated. It is demonstrated that a non critical implant can be used to reduce the forward voltage drop of the transistor for longer drift region devices, and a favourable trade-off between the forward voltage drop and leakage current can be obtained by using the drift region doping. Results on non-optimized devices show that for devices with breakdown voltage of 100V, an 8 times increase in drain to source current in doped CMTFT devices causes only a 30% increase in leakage current compared to the undoped devices.

The effects of offset region doping on the high voltage characteristics of polycrystalline silicon conductivity modulated thin film transistors (CMTFT) are investigated. A non-critical implant can be used to reduce the forward voltage drop of the transistor for longer offset region devices, and a favourable trade-off between the forward voltage drop and leakage current can be obtained by using the offset region doping. An 8 times increase in drain to source current in doped CMTFT devices causes only a 30% increase in leakage current compared to the undoped devices.

The effects of drift region doping on the high voltage (up to 100V) characteristics of the Conductivity Modulated Thin Film Transistor is investigated. It is demonstrated that a non critical implant can be used to reduce the forward voltage drop of the transistor for longer drift region devices, and a favourable trade-off between the forward voltage drop and leakage current can be obtained by using the drift region doping. Results on non-optimized devices show that for devices with breakdown voltage of 100V, an 8 times increase in drain to source current in doped CMTFT devices causes only a 30% increase in leakage current compared to the undoped devices.

The effects of drift region doping on the high voltage (up to 100V) characteristics of the Conductivity Modulated Thin Film Transistor is investigated. It is demonstrated that a non critical implant can be used to reduce the forward voltage drop of the transistor for longer drift region devices, and a favourable trade-off between the forward voltage drop and leakage current can be obtained by using the drift region doping. Results on non-optimized devices show that for devices with breakdown voltage of 100V, an 8 times increase in drain to source current in doped CMTFT devices causes only a 30% increase in leakage current compared to the undoped devices.

The effects of offset region doping on the high voltage characteristics of polycrystalline silicon conductivity modulated thin film transistors (CMTFT) are investigated. A non-critical implant can be used to reduce the forward voltage drop of the transistor for longer offset region devices, and a favourable trade-off between the forward voltage drop and leakage current can be obtained by using the offset region doping. An 8 times increase in drain to source current in doped CMTFT devices causes only a 30% increase in leakage current compared to the undoped devices.

This paper reports the leakage current characteristics of Conductivity Modulated Thin Film Transistor(CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional off-set drain device. The devices were fabricated using a low temperature process(620°C) which is highly desirable for large area electronic applications.

This paper reports the leakage current characteristics of Conductivity Modulated Thin Film Transistor(CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional off-set drain device. The devices were fabricated using a low temperature process(620°C) which is highly desirable for large area electronic applications.

This paper reports the leakage current characteristics of Conductivity Modulated Thin Film Transistor(CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional off-set drain device. The devices were fabricated using a low temperature process(620°C) which is highly desirable for large area electronic applications.

Microstructural evolution and interfacial reactions during active metal vacuum brazing of Ti (grade-2) and stainless steel (SS 304L) using a Ag-based alloy containing Cu, Ti, and Al was investigated. A Ni-depleted solid solution layer and a discontinuous layer of (Ni,Fe)2TiAl intermetallic compound formed on the SS surface and adjacent to the SS-braze alloy interface, respectively. Three parallel contiguous layers of intermetallic compounds, CuTi, AgTi, and (Ag,Cu)Ti2, formed at the Ti-braze alloy interface. The diffusion path for the reaction at this interface was established. Transmission electron microscopy revealed formation of nanocrystals of Ag-Cu alloy of size ranging between 20 and 30 nm in the unreacted braze alloy layer. The interdiffusion zone of β-Ti(Ag,Cu) solid solution, formed on the Ti side of the joint, showed eutectoid decomposition to lamellar colonies of α-Ti and internally twinned (Cu,Ag)Ti2 inter- metallic phase, with an orientation relationship between the two. Bend tests indicated that the failure in the joints occurred by formation and propagation of the crack mostly along the Ti- braze alloy interface, through the (Ag,Cu)Ti2 phase layer.