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This special section is composed of substantially extended handpicked papers from the IEEE Nordic Circuits and Systems Conference (NorCAS) 2022 that took place in October 2022 in Oslo, Norway.

Pushing CMOS technology to the nanometer range is detrimental to analog circuits’ performance due to the reduction of gain and slew rate of amplifiers, so the classical approaches need to be revisited for adjustment in advanced nodes. This paper presents a parallel-path amplifier used as a switched-capacitor (SC) amplifier. The proposed amplifier includes a high bandwidth and slewing path parallel to a high gain path. The high bandwidth and slewing path, named the feedforward path, provides high charging/discharging currents to decrease the slewing time of the amplification phase, significantly (60%). In parallel, the high gain path provides sufficient open-loop DC gain for final settling (59 dB). The feedforward path is enabled/disabled by control signals provided through a hysteresis detector and by considering the status of the feedback voltage. The proposed amplifier is designed and fabricated in 65nm CMOS technology as a multiplying digital-to-analog converter (MDAC) in a pipeline ADC. The chip is under fabrication, and this paper covers post-layout performance of the proposed amplifier. The results reveal that enabling the feedforward path guarantees the amplifier to have a constant error (\lt2 mV) for an extensive range of input voltages (300 mV Vin 900 mV) compared to its standalone high gain path. At the same time, the static current of the feedforward path is minimal (\lt 100 µ A), and it can drive large load capacitors. © 2023 IEEE., Funding: Excellence Center at Linkoping-Lund in Information Technology (ELLIIT)

Extending the wireless power transfer range in miniaturized remotely powered micro-devices is a big challenge due to the very small effective area and low gain of the mm-sized antenna utilized in the micro-devices, which limits the harvested RF energy. This paper presents a method for increasing the separation distance between an external energy source antenna as a transmitter (TX) and micro device antenna as a receiver (RX) beyond 10 cm by utilizing various TX antennas, including a conventional loop antenna, multiple patch antennas, and a rectangular cavity antenna, and a 2-turn double-sided square loop RX antenna, sized 1.2mm x 1.2mm on FR4 substrate, which can be mounted on top of a CMOS SoC. The performance of the wireless power transfer system is evaluated and compared in different scenarios. At the 434 MHz ISM band, the results indicate that the highest peak power transfer efficiency of -20 dB and the highest harvested DC voltage of 4 V through an 8-stage Dickson RF-DC converter are obtained inside the rectangular hollow cavity sized 49.6cm x 49.6cm x 30.4cm, as TX, with an input TX power of 20 dBm. Furthermore, the multiple patch antennas have a power transfer efficiency of -39 dB and a harvested DC voltage of 2.5 V at a distance of 10 cm with an input TX power of 37 dBm. The specific absorption rate of both cases stays below the limits established by IEEE., Funding Agencies|Swedish Foundation for Strategic Research (SSF) [RMX18-0066]

This paper involves the design and integration of an ultra-low power consumption Amplitude Shift Keying (ASK) demodulator and a digital Manchester decoder for biomedical applications. The ASK demodulator is based on a common source (CS) self-biased envelope detector (ED) with a double feedback loop, succeeded by a static comparator featuring constant transistor bias with a native transistor. While the digital Manchester decoder performs clock and data recovery. The practical implementation of the work is validated through simulations, executed on a standard 65 nm CMOS technology with a 50 Kbps data rate and a carrier frequency of 570 MHz. The average current drawn from a 2.5 V power supply is less than 800 nA while the circuit operates under RF variations and modulation indices ranging from 13.5% to 100%., Funding Agencies|Swedish Foundation for Strategic Research (SSF) [RMX18-0066]

© 2022 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0, This paper proposes an all-pass filter-based true time delay (TTD) element covering a 3–5-GHz ultra-wideband (UWB) frequency. The proposed TTD element designed in a standard 0.18-µm CMOS technology achieves a tunable delay range of 385–540 ps with 6-ps delay steps and maximum 11% absolute delay error over a 3–5-GHz frequency band. It exhibits an average 3.6–4.6-dB noise figure (NF) within the whole bandwidth. A four-channel beamforming receiver realized by the proposed TTD element is designed and examined in this paper, as well. With the maximum delay of 540 ps and 6-ps average delay resolution, a maximum steering angle of ±45¿ with 5¿ (18 steps) steering resolution is demonstrated for the beamforming receiver with 2-cm antenna spacing., Peer Reviewed, Postprint (author's final draft)

This paper proposes an all-pass filter-based true time delay (TTD) element covering a 3-5-GHz ultra-wideband (UWB) frequency. The proposed TTD element designed in a standard 0.18-mu m CMOS technology achieves a tunable delay range of 385-540 ps with 6-ps delay steps and maximum 11% absolute delay error over a 3-5-GHz frequency band. It exhibits an average 3.6-4.6-dB noise figure (NF) within the whole bandwidth. A four-channel beamforming receiver realized by the proposed TTD element is designed and examined in this paper, as well. With the maximum delay of 540 ps and 6-ps average delay resolution, a maximum steering angle of +/- 45 degrees with 5 degrees (18 steps) steering resolution is demonstrated for the beamforming receiver with 2-cm antenna spacing.

This paper presents a 4-channel ultra-wideband (UWB) timed array beamforming receiver designed in a standard 0.18-um CMOS technology. The proposed timed array receiver achieves a maximum delay of 250 ps at the maximum beam steering angle of +/-42o with 10.5o (8 steps) steering resolution and 2-cm antenna spacing. Each receiver channel provides gains ranging from 3.6 to -35 dB and less than 8% delay variation for all delay settings over a 3.1-10.6-GHz frequency range, while consuming a maximum of 58 mW power from a 1.8-V supply. The average -1-dB compression point P1dB is -9.9 dBm. The proposed architecture is modeled and simulated by using Virtuoso Cadence., This work has been partially supported by the Spanish Ministerio de Ciencia, Innovacion y Universidades (MICINN)- ´ Agencia Estatal de Investigacion (AEI) and the European ´ Regional Development Funds (FEDER), by project PGC2018- 098946-B-I00., Peer Reviewed, Postprint (author's final draft)

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process., Postprint (published version)

In this paper, a CMOS wideband second-order voltage-mode all-pass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidth of 5 GHz, achieving maximum delay–bandwidth product. The proposed circuit is highly linear and has an input-referred 1-dB compression point P1dB of 2 dBm. The power consumption of the proposed circuit is only 10.3 mW. On the other hand, an active inductor is employed in the all-pass filter instead of a passive RLC tank; therefore, the three passive components are eliminated, in order to tune the time delay and improve the size. In this case, even though the power consumption increases, the time delay can be controlled across an improved bandwidth of approximately 10 GHz. Moreover, the circuit demonstrates a 1-dB compression point P1dB of 18 dBm. The proposed all-pass filter is simulated in TSMC 180-nm CMOS process parameters., Peer Reviewed, Postprint (author's final draft)

Postprint (published version)

In this paper, a wide-band first-order voltage-mode all-pass filter is presented. Due to a simple structure and appropriate performance of the proposed all-pass filter, this filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 4.5 GHz. The proposed circuit demonstrates a high linearity and consumes merely 16 mW power from a 1.8-V supply. Simulation results indicate an input-referred 1-dB compression point P1dB of 4.1 dBm and the wide-band operation capability of the first order all-pass filter. Furthermore, the proposed all-pass filter is capable of converting into a second-order all-pass filter adding only a grounded capacitor. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a TSMC 180-nm CMOS process., Postprint (published version)

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process., Postprint (published version)

A low-quiescent current output-capacitorless class-AB CMOS low-dropout voltage regulator (LDO) capable to source/sink current to/from the load is presented, which is suitable for hybrid or linear-assisted structures utilized in envelope elimination and restoration (EER) applications. The proposed LDO regulator is designed and characterized in 0.18 µm CMOS process to provide a 1 V stable output voltage with 200 mV dropout without any off-chip output capacitor and can deliver a current range of 160 mA between -80 mA and +80 mA to the load, while consumes only 1.8 µA quiescent current., Peer Reviewed, Postprint (published version)

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works., A procedure of extracting a closed-form user-friendly I-V equation for short channel carbon nanotube field-effect transistors (CNFET) in the saturation region is presented by employing a relation between CNFET parameters meeting the experimental results. The methodology is based on the Stanford model and ballistic relation of one channel CNFET. In this regard, the ballistic relation is simplified to a closed-form I-V equation, and then, the parameters are estimated through the fitting algorithm by means of ICCAP and least square (LS) method, respectively, and the obtained equation is verified by the experimental results given in the literature. Additionally, an extended quantitative noise analysis is performed at the circuit level and the noise sources implemented in Verilog-A are added to the Stanford CNFET HSPICE model. Subsequently, with the accordance to the extracted I-V equation, a CNFET-based inductor-less broadband common-gate low noise amplifier (LNA) is designed theoretically and its results are confirmed in HSPICE based on the Stanford CNFET model, indicating a proper matching between analysis and simulation. The proposed CNFET-based LNA provides very high frequency bandwidth and also lower noise figure in comparison with its contemporary CMOS-based LNA, without any passive spiral inductor., Peer Reviewed, Postprint (author's final draft)

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process., Peer Reviewed, Postprint (published version)

This paper presents a selective magnetic resonant wireless power transfer (WPT) system, consisting of a transmitter (TX), a tunable intermediate-resonator, and a receiver (RX). In the proposed WPT system, the tunable intermediate-resonator can be either a relay resonator or an intermediate-RX by varying its variable resistance, demonstrating the flexibility of the intermediate resonator to be used for different topologies and applications. This flexibility will enable the proposed WPT system to transfer maximum energy efficiency to various distances between the TX and the RX, to longer distances for the WPT relay system and to shorter distances for the intermediate-RX system. In this case, the WPT intermediate-RX system has a larger power transfer efficiency than the WPT relay system., Postprint (published version)

This paper presents an approach to utilize of sliding-mode (SM) controller in digital low-dropout/linear regulators. Various design aspects, including the extraction of the regulator state-space model and sliding coefficients by considering the hitting, existence, and stability conditions are described. Moreover, the freeze control block is introduced as a solution to compensate the high frequency chattering phenomenon of SM, resulting in reduction of switching losses. In order to verify the statements, a quasi digital low-dropout/linear regulator (QDLDO) is implemented in a discrete form on a PCB. The circuit consists of the proposed current-mode current feedback amplifier (CFA)-based SM controller and switchedmode PMOS array driven by a bidirectional serial shift register, which is controlled by the SM controller. The results reveal that the controller detects the load changes rapidly, and eliminates the output limit-cycle oscillation, providing a robust and stable output voltage., Peer Reviewed, Postprint (author's final draft)

Peer Reviewed, Postprint (published version)

This paper presents a CMOS RF second-order voltage-mode all-pass filter (APF) as a time delay cell. The proposed filter benefits from a simple structure; consisting of one transistor, three resistors, and one grounded capacitor and inductor. The filter reaches a group delay of 60 ps over a 10 GHz bandwidth, while achieving maximum delay-bandwidth-product (DBW) and it consumes only 10.3 mW power. On the other hand, an active inductor is used in the APF instead of a passive RLC tank in order to control the time delay and improve the size. In this case, the power consumption increases while time delay can be tuned. The proposed APF is designed and simulated in a TSMC 180 nm CMOS process., Postprint (published version)

This paper presents an output-capacitorless class-AB low-dropout (LDO) regulator with load current sinking and sourcing ability. The proposed LDO consists of two complementary pass transistors, controlled using a level shifter technique. The transient improvement section applied to the gates of the pass devices enhances the transient performance of the LDO. The proposed LDO is designed in TSMC 0.18 µm CMOS process with input and output voltages of 1.2-2.5 V and 1 V, respectively, 10 pF output capacitor, and quiescent current of 3.14 µA, and is capable to sink and source maximum load currents of ±100 mA, giving the current efficiency of 99.99%., Peer Reviewed, Postprint (published version)

A proposal of current source based on a linear-assisted DC/DC converter is presented, in which a linear voltage regulator assists a switching DC/DC converter in order to obtain a compact circuit with advantages of both alternatives; i.e. high efficiency (similar to the switching converter), and low output ripple and fast reaction to the load changes (similar to the linear regulator). To reduce the power dissipation in the linear regulator, it is considered as an assisted circuit for providing just a little fraction of the load current. Furthermore, this stage provides the required clock signal for the switching counterpart, resulting in reduction of the complexity in the design of the control scheme for the switching converter and a compact topology, especially for on-chip practical implementations, since no output capacitors are required. This last advantage provides the possibility of obtaining good-performance current-source drivers for LED technology in lighting applications. The implementation and results indicate that the proposed linear-assisted DC/DC regulator-based current source can achieve a notably compacting and higher performance, while consuming less power in comparison to linear alternatives., Peer Reviewed, Postprint (author's final draft)

This paper deals with a circuit proposal along with theoretical analysis to provide a solution for enhancing the stability and transient performance of external capacitorless low-dropout regulators (CL-LDOs) by segmenting the pass transistor to smaller sizes. The stability and transient analysis is carried out on the CL-LDO with two different size-segmented pass transistors in comparison with the conventional CL-LDO with single large size pass device. The analysis shows that the pass transistor segmentation leads to better stability, i.e., greater phase margin especially at no-load and light-load conditions, wider bandwidth, and improved transient behavior, i.e., lower settling time and output voltage deviations due to the load transients. The aforementioned topologies are modeled and validated in HSPICE using a 0.35 µm CMOS process, and the results are in conformity with the analytical statements., Peer Reviewed, Postprint (published version)

In this paper, a new structure based on linear-assisted DC-DC buck converter principle is proposed. Using a new class-AB LDO regulator instead of the conventional linear one (based on a push-pull output stage) in the hybrid scheme, reduces the difference between input and output voltages and also the switching frequency of the buck converter. Thus, the proposal achieves higher power efficiency rather than the conventional linear-assisted converter, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. In addition, the circuit provides a lower output ripple and better transient response. A comparison analysis is done with regards to the considered performance indexes between the proposed structure and linear-assisted buck converter, and the results are validated in HSPICE in a 0.35 µm CMOS process., Peer Reviewed, Postprint (published version)

This article presents a low quiescent current output capacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively., Postprint (published version)

This Mixed Signal Letter presents a proposal of four-quadrant linear-assisted DC/DC voltage regulator. In this topology, a class-AB linear voltage amplifier assists a four-quadrant switching DC/DC converter in order to obtain a compact circuit with advantages of both alternatives; i.e., high efficiency, inherent in switching converters, and low output ripple and fast reaction to the load changes that are characteristics of linear regulators. In order to reduce the power dissipation in the linear regulator, it is considered as an assisting circuit for providing just a small fraction of the total load current. Furthermore, this stage provides the required clock signal for the switching counterpart, obtaining a compact topology thanks to the reduction of the complexity in the design of the control scheme for the switching converter. In fact, the proposed topology can be addressed to on-chip practical implementations, since no output capacitors are required. This last advantage provides the possibility of obtaining good-performance power-supply modulators for envelope tracking techniques in power amplifiers. The implementation and results indicate that the proposed four-quadrant linear-assisted DC/DC regulator can achieve a notably compacting and higher performance, while consuming less power in comparison to linear alternatives., Postprint (author's final draft)

This paper deals with a comprehensive study and comparison on the conventional linear-assisted converter and a new structure named, LDO-assisted converter based on a new class-AB LDO regulator instead of the conventional linear one, in terms of efficiency, output ripple, and load transient response. The new structure reduces difference between input and output voltages and also switching frequency of the buck converter, corresponding to higher power efficiency, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. A comparison analysis is done and the results are validated in HSPICE in a 0.18 µm CMOS process., Postprint (published version)

© The Institution of Engineering and Technology 2016. A proposal of current source based on a linear-assisted DC/DC converter is presented, in which a linear voltage regulator assists a switching DC/DC converter in order to obtain a compact circuit with advantages of both alternatives; i.e. high efficiency (similar to the switching converter), and low output ripple and fast reaction to the load changes (similar to the linear regulator). To reduce the power dissipation in the linear regulator, it is considered as an assisted circuit for providing just a little fraction of the load current. Furthermore, this stage provides the required clock signal for the switching counterpart, resulting in reduction of the complexity in the design of the control scheme for the switching converter and a compact topology, especially for onchip practical implementations, since no output capacitors are required. This last advantage provides the possibility of obtaining good-performance current-source drivers for LED technology in lighting applications. The implementation and results indicate that the proposed linear-assisted DC/DC regulator-based current source can achieve a notably compacting and higher performance, while consuming less power in comparison to linear alternatives., Postprint (published version)

Postprint (published version)

This article presents a low quiescent current outputcapacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively., Postprint (published version)

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18¿µm CMOS process to supply a stable load current between 0 and 100¿mA with a 40¿pF on-chip output capacitor, while consuming 4.8¿µA quiescent current. The dropout voltage of the LDO is set to 200¿mV for 1.8¿V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively., Postprint (author's final draft)

This paper proposes the use of double-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells as a candidate topology for envelope elimination and restoration (EER) applications and integrated power Supply of RF power amplifiers (RFPA) to obtain favorable tradeoffs in terms of efficiency, switching ripple, bandwidth, and tracking capability. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency, low output ripples, and tracking capability with low ripples, simultaneously. A comparison analysis is done with regards to the mentioned performance indexes with the standard and three-level buck converters; in addition, the results are validated in HSPICE in BSIM3V3 0.35-µm CMOS process., Postprint (author's final draft)

This paper deals with a comprehensive study and comparison on the conventional linear-assisted converter and a new structure named, LDO-assisted converter based on a new class-AB LDO regulator instead of the conventional linear one, in terms of efficiency, output ripple, and load transient response. The new structure reduces difference between input and output voltages and also switching frequency of the buck converter, corresponding to higher power efficiency, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. A comparison analysis is done and the results are validated in HSPICE in a 0.18 µm CMOS process., Peer Reviewed, Postprint (published version)

This Mixed Signal Letter presents a proposal of four-quadrant linear-assisted DC/DC voltage regulator. In this topology, a class-AB linear voltage amplifier assists a four-quadrant switching DC/DC converter in order to obtain a compact circuit with advantages of both alternatives; i.e., high efficiency, inherent in switching converters, and low output ripple and fast reaction to the load changes that are characteristics of linear regulators. In order to reduce the power dissipation in the linear regulator, it is considered as an assisting circuit for providing just a small fraction of the total load current. Furthermore, this stage provides the required clock signal for the switching counterpart, obtaining a compact topology thanks to the reduction of the complexity in the design of the control scheme for the switching converter. In fact, the proposed topology can be addressed to on-chip practical implementations, since no output capacitors are required. This last advantage provides the possibility of obtaining good-performance power-supply modulators for envelope tracking techniques in power amplifiers. The implementation and results indicate that the proposed four-quadrant linear-assisted DC/DC regulator can achieve a notably compacting and higher performance, while consuming less power in comparison to linear alternatives., Postprint (author's final draft)

Peer Reviewed, Postprint (author's final draft)

Peer Reviewed, Postprint (author's final draft)

Peer Reviewed, Postprint (author's final draft)

In this paper, a new structure based on linear-assisted DC-DC buck converter principle is proposed. Using a segmented LDO regulator instead of the conventional linear one in the hybrid scheme, reduces the difference between input and output voltages and also the switching frequency of the buck converter, while the circuit provides a lower output ripple, better transient response. In addition, the proposal achieves higher power efficiency rather than the linear-assisted converter, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. A comparison analysis is done with regards to the mentioned performance indexes between the proposed structure and linear-assisted buck converter and the results are validated in HSPICE in a 0.35 µm CMOS process., Peer Reviewed, Postprint (published version)

Postprint (published version)

This paper presents an output-capacitorless low dropout (LDO) regulator based on improved flipped voltage follower power stage for use in power management circuits. A new error amplifier (EA) structure, named as gain-bandwidth enhanced EA, is embedded in the LDO regulator. The LDO regulator is designed for the input and output voltages of 1.2 V and 1 V, respectively. Fast transients, low overshoot and undershoot, and low quiescent current of 6 µA are achieved for the proposed circuit. The LDO regulator is designed for maximum load current of 50 mA, achieving the current and power efficiencies of 99.99% and 83.3%, respectively. Additionally, up to 131 pF capacitance is used in the proposed LDO structure. The proposed circuit is designed and verified in HSPICE in TSMC 0.18 µm mixed signal CMOS process., Peer Reviewed, Postprint (published version)

Peer Reviewed, Postprint (published version)

Postprint (published version)

Buck converter; efficiency; LDO-assisted; linear-assisted; output ripple., Postprint (published version)

This paper proposes the use of double-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells as a candidate topology for envelope elimination and restoration (EER) applications and integrated power supply of RF power amplifiers (RFPA) to obtain favorable tradeoffs in terms of efficiency, switching ripple, bandwidth, and tracking capability. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency, low output ripples, and tracking capability with low ripples, simultaneously. A comparison analysis is done with regards to the mentioned performance indexes with the standard and three-level buck converters; in addition, the results are validated in HSPICE in BSIM3V3 0.35-µm CMOS process., Peer Reviewed, Postprint (author's final draft)

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18¿µm CMOS process to supply a stable load current between 0 and 100¿mA with a 40¿pF on-chip output capacitor, while consuming 4.8¿µA quiescent current. The dropout voltage of the LDO is set to 200¿mV for 1.8¿V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively., Peer Reviewed, Postprint (author's final draft)

This paper presents the use of a new structure of active inductor named cascoded flipped-active inductor (CASFAI) in a T-type high-pass tunable output matching network of a class-E RF power amplifier (RFPA) to control the output power and enhance the efficiency. The designed CASFAI behaves as an inductor in the frequency range of 0–6.9 GHz, and has reached to a maximum quality factor of 4406, inductance value of 7.56 nH, 3rd order harmonic distortion better than -30 dB for 0 dBm input power, while consumes only 2 mW power. In order to consider the performance of the proposed active inductor-based tunable output matching network on the output power level and power added efficiency (PAE) of RFPA, the CASFAI is applied as a variable inductor to the output matching network of RFPA. The overall circuit is designed and validated in ADS in a 0.18 µm CMOS process and 1.5 V supply voltage. The results indicate that by increasing the inductance value of the matching network in constant operating frequency, the PAE peak moves from high power to low power levels without any degradation. Therefore, it is possible to maintain the power efficiency at the same maximum level for lower input drive levels., Peer Reviewed, Postprint (author's final draft)

This article presents a fully-integrated CMOS output-capacitorless low-dropout voltage regulator (LDO). A capacitor multiplier based on a current-mode amplifier is embedded into the error amplifier of the aforementioned LDO to simultaneously enhance the dynamic specifications to load variations, stability by pole splitting, and power saving. The proposed LDO topology is designed and post simulated using a 0.35 mu m CMOS process to deliver a load current between 0-100 mA. The dropout voltage of the LDO is set to 200 mV for 2-3.5 V input voltage. A final benchmark comparison considering all relevant performance metrics is presented., Peer Reviewed, Postprint (author’s final draft)

The use of dual-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells is presented as a candidate topology for integrated power management to obtain favorable tradeoffs in terms of efficiency, switching ripple, and bandwidth. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency and low output ripples, simultaneously. A comparison analysis is done with regards to the aforementioned performance indexes with the standard and three-level buck converters and the results are validated in HSPICE in a 0.35 µm CMOS process., Peer Reviewed, Postprint (published version)

A new design based on the flipped-structure for RF active inductors is presented. The conventional flipped-active inductor (FAI) composed of only two transistors is considered as a starting structure. However, it suffers from low-voltage swing, which increases the nonlinearity. Additionally, it requires high power consumption to achieve adequate inductance and quality factor values. A circuit topology named cascoded FAI (CASFAI) based on the basic FAI is proposed. A common-gate transistor added in the feedback path of the proposed CASFAI results in an increase of the voltage swing and linearity as well as the feedback gain. The performance metrics of such active inductors are benchmarked by analytical models and validated in the ADS using a 0.18 µm CMOS process. The results indicate that the CASFAI can achieve a notably higher quality factor and higher inductance values while consuming less power in comparison to the basic FAI., Postprint (published version)

A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 μm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF., Postprint (published version)

This paper presents a current-steering approach to implement a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) topology. The circuit does not require any internal compensation capacitor, being stable for a wide range of output load currents [0–100 mA] and a 1 μF output capacitor. The CFA consists of an open-loop voltage follower with output local current–current feedback based on a level-shifted flipped voltage follower (LSFVF) which is instrumental to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. Post-layout simulation results for a 0.35 μm CMOS process design reveal that the proposed LDO requires 59 μA quiescent current at no-load condition and at full-load condition has a current efficiency of 99.8%. For a 1 μF output capacitor, the maximum output voltage variation to a 0–100 mA load transient with rise and fall times of 10 and 100 ns is only 3 mV, and the PSRR is smaller than −56 dB over the entire load current range., Peer Reviewed, Postprint (published version)